| /netbsd-src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| H A D | bcm59056.dtsi | 67 vsr_reg: vsr {
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/ |
| H A D | amdgpu_dce_calcs.c | 477 data->vsr[i] = bw_mul(data->vsr_after_stereo, bw_int_to_fixed(2)); in calculate_bandwidth()
480 data->vsr[i] = data->vsr_after_stereo; in calculate_bandwidth()
531 if (bw_neq(data->vsr[i], bw_int_to_fixed(1))) { in calculate_bandwidth()
532 if (bw_mtn(data->vsr[i], bw_int_to_fixed(4))) { in calculate_bandwidth()
536 if (bw_mtn(data->vsr[i], data->v_taps[i])) { in calculate_bandwidth()
795 …), data->v_taps[i]), data->vsr[i]), bw_mul(bw_mul(bw_int_to_fixed(data->interlace_mode[i]), bw_frc… in calculate_bandwidth()
812 …if ((bw_mtn(data->vsr[i], bw_int_to_fixed(1)) && surface_type[i] == bw_def_graphics) || data->pann… in calculate_bandwidth()
815 … && (bw_mtn(data->lb_partitions[i], bw_add(data->v_taps[i], bw_ceil2(data->vsr[i], bw_int_to_fixed… in calculate_bandwidth()
823 … data->lb_lines_in_per_line_out_in_middle_of_frame[i] = bw_max2(bw_int_to_fixed(1), data->vsr[i]); in calculate_bandwidth()
825 else if (bw_leq(data->vsr[i], bw_int_to_fixed(1))) { in calculate_bandwidth()
[all …]
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| H A D | calcs_logger.h | 441 DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] vsr[%d]:%d", i, bw_fixed_to_int(data->vsr[i])); in print_bw_calcs_data()
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| /netbsd-src/external/gpl3/gcc/dist/gcc/d/dmd/ |
| H A D | escape.d | 1287 … void escapingRef(VarDeclaration v, ScopeRef vsr, FeatureState featureState = FeatureState.enabled) in checkReturnEscapeImpl()
1316 const vsr = buildScopeRef(v.storage_class); in checkReturnEscapeImpl() local
1328 escapingRef(v, vsr, FeatureState.enabled); in checkReturnEscapeImpl()
1351 if ((vsr == ScopeRef.Ref || in checkReturnEscapeImpl()
1352 vsr == ScopeRef.RefScope || in checkReturnEscapeImpl()
1353 vsr == ScopeRef.Ref_ReturnScope) && in checkReturnEscapeImpl()
1357 (vsr == ScopeRef.Ref || vsr == ScopeRef.RefScope)) in checkReturnEscapeImpl()
1369 escapingRef(v, vsr, global.params.useDIP25); in checkReturnEscapeImpl()
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| /netbsd-src/external/gpl3/gdb/dist/gdb/testsuite/gdb.base/ |
| H A D | constvars.c | 15 volatile short /*&*/vsr, volatile long *vlp, float *volatile fpv, in qux2()
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| /netbsd-src/external/gpl3/gdb.old/dist/gdb/testsuite/gdb.base/ |
| H A D | constvars.c | 15 volatile short /*&*/vsr, volatile long *vlp, float *volatile fpv, in qux2()
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| /netbsd-src/crypto/external/bsd/openssl/dist/crypto/perlasm/ |
| H A D | ppc-xlate.pl | 202 my $vsr = sub { vsr2vr("vsr", 3, @_); };
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/ |
| H A D | dce_calcs.h | 405 struct bw_fixed vsr[maximum_number_of_surfaces]; member
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/IR/ |
| H A D | IntrinsicsPowerPC.td | 995 def int_ppc_altivec_vsr : PowerPC_Vec_WWW_Intrinsic<"vsr">;
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| /netbsd-src/external/gpl3/gcc.old/dist/gcc/config/rs6000/ |
| H A D | vector.md | 1413 ;; General shift amounts can be supported using vsro + vsr. We're
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| H A D | altivec.md | 1743 "vsr<VI_char> %0,%1,%2"
1760 "vsr %0,%1,%2"
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| H A D | rs6000-builtin.def | 1305 BU_ALTIVEC_2 (VSR, "vsr", CONST, altivec_vsr)
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| /netbsd-src/external/gpl3/gcc/dist/gcc/config/rs6000/ |
| H A D | vector.md | 1538 ;; General shift amounts can be supported using vsro + vsr. We're
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| H A D | altivec.md | 2033 "vsr<VI_char> %0,%1,%2"
2068 "vsr %0,%1,%2"
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrAltivec.td | 723 def VSR : VX1_Int_Ty< 708, "vsr" , int_ppc_altivec_vsr, v4i32>;
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| /netbsd-src/external/gpl3/gcc/dist/gcc/ |
| H A D | ChangeLog-2001 | 6332 (vsr): New.
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| /netbsd-src/external/gpl3/binutils/dist/ |
| H A D | ChangeLog.git | 16937 register (vsr).
16942 actually stored in a vsr not the fprs. This patch changes the register
16943 mapping for the vsrs from the fpr to the vsr registers so the value is
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