Searched refs:umc (Results 1 – 10 of 10) sorted by relevance
42 if (!adev->umc.ras_if) { in amdgpu_umc_ras_late_init()43 adev->umc.ras_if = in amdgpu_umc_ras_late_init()45 if (!adev->umc.ras_if) in amdgpu_umc_ras_late_init()47 adev->umc.ras_if->block = AMDGPU_RAS_BLOCK__UMC; in amdgpu_umc_ras_late_init()48 adev->umc.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in amdgpu_umc_ras_late_init()49 adev->umc.ras_if->sub_block_index = 0; in amdgpu_umc_ras_late_init()50 strcpy(adev->umc.ras_if->name, "umc"); in amdgpu_umc_ras_late_init()52 ih_info.head = fs_info.head = *adev->umc.ras_if; in amdgpu_umc_ras_late_init()54 r = amdgpu_ras_late_init(adev, adev->umc.ras_if, in amdgpu_umc_ras_late_init()59 if (amdgpu_ras_is_supported(adev, adev->umc.ras_if->block)) { in amdgpu_umc_ras_late_init()[all …]
801 adev->umc.funcs = &umc_v6_0_funcs; in gmc_v9_0_set_umc_funcs()804 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; in gmc_v9_0_set_umc_funcs()805 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; in gmc_v9_0_set_umc_funcs()806 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; in gmc_v9_0_set_umc_funcs()807 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_VG20; in gmc_v9_0_set_umc_funcs()808 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; in gmc_v9_0_set_umc_funcs()809 adev->umc.funcs = &umc_v6_1_funcs; in gmc_v9_0_set_umc_funcs()812 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; in gmc_v9_0_set_umc_funcs()813 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; in gmc_v9_0_set_umc_funcs()814 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; in gmc_v9_0_set_umc_funcs()[all …]
50 #define LOOP_UMC_INST(umc_inst) for ((umc_inst) = 0; (umc_inst) < adev->umc.umc_inst_num; (umc_inst…51 #define LOOP_UMC_CH_INST(ch_inst) for ((ch_inst) = 0; (ch_inst) < adev->umc.channel_inst_num; (ch_i…90 return adev->umc.channel_offs*ch_inst + UMC_6_INST_DIST*umc_inst; in get_umc_6_reg_offset()220 …uint32_t channel_index = adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst… in umc_v6_1_query_error_address()
339 if (adev->umc.funcs && adev->umc.funcs->ras_late_init) { in amdgpu_gmc_ras_late_init()340 r = adev->umc.funcs->ras_late_init(adev); in amdgpu_gmc_ras_late_init()
707 if (adev->umc.funcs->query_ras_error_count) in amdgpu_ras_error_query()708 adev->umc.funcs->query_ras_error_count(adev, &err_data); in amdgpu_ras_error_query()712 if (adev->umc.funcs->query_ras_error_address) in amdgpu_ras_error_query()713 adev->umc.funcs->query_ras_error_address(adev, &err_data); in amdgpu_ras_error_query()
927 struct amdgpu_umc umc; member
1031 (define-pmacro (set-psw.umc zval) (set-bit (raw-reg h-csr 16) 2 zval))2000 (set-psw.umc (get-psw.ump))2005 (set-psw.umc (get-psw.ump))