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Searched refs:tx_conf_read (Results 1 – 18 of 18) sorted by relevance

/netbsd-src/sys/arch/hpcmips/tx/
H A Dtx39icu.c234 regs[0] = tx_conf_read(tc, TX39_INTRSTATUS6_REG); in tx39icu_attach()
235 regs[1] = tx_conf_read(tc, TX39_INTRSTATUS1_REG); in tx39icu_attach()
236 regs[2] = tx_conf_read(tc, TX39_INTRSTATUS2_REG); in tx39icu_attach()
237 regs[3] = tx_conf_read(tc, TX39_INTRSTATUS3_REG); in tx39icu_attach()
238 regs[4] = tx_conf_read(tc, TX39_INTRSTATUS4_REG); in tx39icu_attach()
239 regs[5] = tx_conf_read(tc, TX39_INTRSTATUS5_REG); in tx39icu_attach()
241 regs[7] = tx_conf_read(tc, TX39_INTRSTATUS7_REG); in tx39icu_attach()
242 regs[8] = tx_conf_read(tc, TX39_INTRSTATUS8_REG); in tx39icu_attach()
264 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG); in tx39icu_attach()
271 tx_conf_read(tc, TX39_INTRSTATUS1_REG)); in tx39icu_attach()
[all …]
H A Dtx39spi.c76 reg = tx_conf_read(tc, TX39_SPICTRL_REG); in tx39spi_attach()
138 return tx_conf_read(sc->sc_tc, TX39_SPICTRL_REG) & (TX39_SPICTRL_EMPTY); in tx39spi_is_empty()
146 while(!(tx_conf_read(tc, TX39_INTRSTATUS5_REG) & TX39_INTRSTATUS5_SPIBUFAVAILINT)) in tx39spi_put_word()
158 while(!(tx_conf_read(tc, TX39_INTRSTATUS5_REG) & TX39_INTRSTATUS5_SPIRCVINT)) in tx39spi_get_word()
162 return tx_conf_read(tc, TX39_SPIRXHOLD_REG) & 0xffff; in tx39spi_get_word()
169 txreg_t reg = tx_conf_read(tc, TX39_SPICTRL_REG); in tx39spi_enable()
181 txreg_t reg = tx_conf_read(tc, TX39_SPICTRL_REG); in tx39spi_delayval()
189 txreg_t reg = tx_conf_read(tc, TX39_SPICTRL_REG); in tx39spi_baudrate()
197 txreg_t reg = tx_conf_read(tc, TX39_SPICTRL_REG); in tx39spi_word()
209 txreg_t reg = tx_conf_read(tc, TX39_SPICTRL_REG); in tx39spi_phapol()
[all …]
H A Dtx39power.c111 reg = tx_conf_read(tc, TX39_POWERCTRL_REG); in tx39power_attach()
116 reg = tx_conf_read(tc, TX39_POWERCTRL_REG); in tx39power_attach()
157 reg = tx_conf_read(tc, TX39_POWERCTRL_REG); in tx39power_suspend_cpu()
160 iregs[0] = tx_conf_read(tc, TX39_INTRENABLE6_REG); in tx39power_suspend_cpu()
161 iregs[1] = tx_conf_read(tc, TX39_INTRENABLE1_REG); in tx39power_suspend_cpu()
162 iregs[2] = tx_conf_read(tc, TX39_INTRENABLE2_REG); in tx39power_suspend_cpu()
163 iregs[3] = tx_conf_read(tc, TX39_INTRENABLE3_REG); in tx39power_suspend_cpu()
164 iregs[4] = tx_conf_read(tc, TX39_INTRENABLE4_REG); in tx39power_suspend_cpu()
165 iregs[5] = tx_conf_read(tc, TX39_INTRENABLE5_REG); in tx39power_suspend_cpu()
167 iregs[7] = tx_conf_read(tc, TX39_INTRENABLE7_REG); in tx39power_suspend_cpu()
[all …]
H A Dtx39clock.c123 reg = tx_conf_read(tc, TX39_TIMERCONTROL_REG); in tx39clock_attach()
180 reg = tx_conf_read(tc, TX39_TIMERCONTROL_REG); in __tx39timer_rtcfreeze()
204 oreglo = tx_conf_read(tc, TX39_TIMERRTCLO_REG); in __tx39timer_rtcget()
205 reglo = tx_conf_read(tc, TX39_TIMERRTCLO_REG); in __tx39timer_rtcget()
207 oreghi = tx_conf_read(tc, TX39_TIMERRTCHI_REG); in __tx39timer_rtcget()
208 reghi = tx_conf_read(tc, TX39_TIMERRTCHI_REG); in __tx39timer_rtcget()
224 reg = tx_conf_read(tc, TX39_TIMERCONTROL_REG); in __tx39timer_rtcreset()
246 return tx_conf_read(tc, TX39_TIMERRTCLO_REG); in tx39_timecount()
261 reg = tx_conf_read(tc, TX39_TIMERPERIODIC_REG); in tx39clock_init()
269 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG); in tx39clock_init()
[all …]
H A Dtx39io.c230 reg = tx_conf_read(tc, TX39_IOMFIODATAOUT_REG); in mfio_out()
244 return (tx_conf_read(sc->sc_tc, TX39_IOMFIODATAIN_REG) & (1 << port)); in mfio_in()
272 stat_mfio->dir = tx_conf_read(tc, TX39_IOMFIODATADIR_REG); in mfio_update()
273 stat_mfio->in = tx_conf_read(tc, TX39_IOMFIODATAIN_REG); in mfio_update()
274 stat_mfio->out = tx_conf_read(tc, TX39_IOMFIODATAOUT_REG); in mfio_update()
275 stat_mfio->power = tx_conf_read(tc, TX39_IOMFIOPOWERDWN_REG); in mfio_update()
276 stat_mfio->u.select = tx_conf_read(tc, TX39_IOMFIODATASEL_REG); in mfio_update()
287 txreg_t reg = tx_conf_read(sc->sc_tc, TX39_IOCTRL_REG); in tx391x_io_in()
312 reg = tx_conf_read(tc, TX39_IOCTRL_REG); in tx391x_io_out()
333 reg = tx_conf_read(tc, TX39_IOCTRL_REG); in tx391x_io_update()
[all …]
H A Dtx39sib.c207 reg = tx_conf_read(tc, TX39_SIBDMACTRL_REG); in tx39sib_enable1()
217 reg = tx_conf_read(tc, TX39_SIBCTRL_REG); in tx39sib_enable1()
229 reg = tx_conf_read(tc, TX39_SIBCTRL_REG); in tx39sib_enable2()
244 reg = tx_conf_read(tc, TX39_SIBCTRL_REG); in tx39sib_disable()
251 reg = tx_conf_read(tc, TX39_SIBCTRL_REG); in tx39sib_disable()
315 for (i = 0; (!(tx_conf_read(tc, TX39_INTRSTATUS1_REG) & in __txsibsf0_ready()
362 reg = tx_conf_read(tc, TX39_SIBSF0STAT_REG); in txsibsf0_read()
384 reg = tx_conf_read(tc, TX39_SIBCTRL_REG); in tx39sib_dump()
405 reg = tx_conf_read(tc, TX39_SIBDMACTRL_REG); in tx39sib_dump()
H A Dtx39biu.c101 reg = tx_conf_read(tc, TX39_MEMCONFIG4_REG); in tx39biu_attach()
106 reg = tx_conf_read(tc, TX39_MEMCONFIG4_REG); in tx39biu_attach()
154 reg = tx_conf_read(tc, TX39_MEMCONFIG4_REG); in tx39biu_intr()
157 reg = tx_conf_read(tc, TX39_MEMCONFIG4_REG); in tx39biu_intr()
179 reg = tx_conf_read(tc, TX39_MEMCONFIG0_REG); in tx39biu_dump()
229 reg = tx_conf_read(tc, TX39_MEMCONFIG3_REG); in tx39biu_dump()
257 reg = tx_conf_read(tc, TX39_MEMCONFIG4_REG); in tx39biu_dump()
H A Dtxcom.c318 reg = tx_conf_read(tc, TX39_CLOCKCTRL_REG); in txcom_reset()
348 reg = tx_conf_read(tc, TX39_CLOCKCTRL_REG); in txcom_enable()
355 reg = tx_conf_read(tc, ofs); in txcom_enable()
360 reg = tx_conf_read(tc, ofs); in txcom_enable()
367 while(!(tx_conf_read(tc, ofs) & TX39_UARTCTRL1_UARTON) && in txcom_enable()
389 reg = tx_conf_read(tc, TX39_UARTCTRL1_REG(slot)); in txcom_disable()
398 reg = tx_conf_read(tc, TX39_CLOCKCTRL_REG); in txcom_disable()
411 if (tx_conf_read(tc, ofs) & TX39_UARTCTRL1_EMPTY) in __txcom_txbufready()
429 reg = tx_conf_read(tc, ofs); in txcom_pulse_mode()
452 while(!(TX39_UARTCTRL1_RXHOLDFULL & tx_conf_read(t in txcom_cngetc()
[all...]
H A Dtxcsbus.c278 reg = tx_conf_read(tc, TX39_MEMCONFIG0_REG); in __txcsbus_alloc_cstag()
286 reg = tx_conf_read(tc, TX39_MEMCONFIG1_REG); in __txcsbus_alloc_cstag()
297 reg = tx_conf_read(tc, TX39_MEMCONFIG0_REG); in __txcsbus_alloc_cstag()
303 reg = tx_conf_read(tc, TX39_MEMCONFIG1_REG); in __txcsbus_alloc_cstag()
311 reg = tx_conf_read(tc, TX39_MEMCONFIG3_REG); in __txcsbus_alloc_cstag()
332 reg = tx_conf_read(tc, TX39_MEMCONFIG3_REG); in __txcsbus_alloc_cstag()
H A Dtx39ir.c97 reg = tx_conf_read(tc, TX39_IRCTRL1_REG); in tx39ir_attach()
102 reg = tx_conf_read(tc, TX39_CLOCKCTRL_REG); in tx39ir_attach()
130 reg = tx_conf_read(tc, TX39_IRCTRL1_REG); in tx39ir_dump()
H A Dtx3912video.c157 val = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); in tx3912video_attach()
220 val = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); in tx3912video_power()
228 val = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); in tx3912video_power()
308 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); in tx3912video_init()
319 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); in tx3912video_init()
406 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); in tx3912video_framebuffer_init()
445 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); in tx3912video_resolution_init()
476 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); in tx3912video_reset()
H A Dtx39var.h95 #define tx_conf_read(t, reg) ( \ macro
H A Dtx39.c134 rev = tx_conf_read(tc, TX3922_REVISION_REG); in tx_init()
/netbsd-src/sys/arch/hpcmips/dev/
H A Dteliosio.c230 reg = tx_conf_read(tc, TX392X_IODATAINOUT_REG); in teliosio_ac_state()
259 reg = tx_conf_read(tc, TX392X_IODATAINOUT_REG); in teliosio_mbu_write()
270 reg = tx_conf_read(tc, TX392X_IODATAINOUT_REG); in teliosio_mbu_write()
288 reg = tx_conf_read(tc, TX392X_IODATAINOUT_REG); in teliosio_mbu_read()
295 reg = tx_conf_read(tc, TX392X_IODATAINOUT_REG); in teliosio_mbu_read()
H A Ducbsnd.c288 reg = tx_conf_read(tc, TX39_SIBCTRL_REG); in ucbsnd_exec_output()
305 reg = tx_conf_read(tc, TX39_SIBSF0STAT_REG); in ucbsnd_exec_output()
372 reg = tx_conf_read(tc, TX39_SIBDMACTRL_REG); in ucbsnd_exec_output()
443 reg = tx_conf_read(tc, TX39_SIBSF0STAT_REG); in ucbsnd_exec_output()
467 reg = tx_conf_read(tc, TX39_SIBCTRL_REG); in ucbsnd_exec_output()
H A Dit8368.c553 reg32 = tx_conf_read(sc->sc_tc, TX39_MEMCONFIG3_REG); in it8368_mode()
575 reg32 = tx_conf_read(sc->sc_tc, TX39_MEMCONFIG3_REG); in it8368_mode()
H A Ducbtp.c578 reg = tx_conf_read(tc, TX39_SIBSF0STAT_REG); in ucbtp_adc_async()
/netbsd-src/sys/arch/hpcmips/stand/pbsdboot/
H A Dtx39xx.c51 tx_conf_read(tx_chipset_tag_t t, int reg) in tx_conf_read() function