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Searched refs:timing (Results 1 – 25 of 436) sorted by relevance

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/netbsd-src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/bios/
H A Dnouveau_nvkm_subdev_bios_timing.c38 u32 timing = 0; in nvbios_timingTe() local
42 timing = nvbios_rd32(bios, bit_P.offset + 4); in nvbios_timingTe()
45 timing = nvbios_rd32(bios, bit_P.offset + 8); in nvbios_timingTe()
47 if (timing) { in nvbios_timingTe()
48 *ver = nvbios_rd08(bios, timing + 0); in nvbios_timingTe()
51 *hdr = nvbios_rd08(bios, timing + 1); in nvbios_timingTe()
52 *cnt = nvbios_rd08(bios, timing + 2); in nvbios_timingTe()
53 *len = nvbios_rd08(bios, timing + 3); in nvbios_timingTe()
56 return timing; in nvbios_timingTe()
58 *hdr = nvbios_rd08(bios, timing + 1); in nvbios_timingTe()
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/netbsd-src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/fb/
H A Dnouveau_nvkm_subdev_fb_ramnv50.c78 nv50_ram_timing_calc(struct nv50_ram *ram, u32 *timing) in nv50_ram_timing_calc() argument
103 timing[6] = (0x2d + T(CL) - T(CWL) + in nv50_ram_timing_calc()
109 timing[6] = (0x2b + T(CL) - T(CWL)) << 16 | in nv50_ram_timing_calc()
114 timing[0] = (T(RP) << 24 | T(RAS) << 16 | T(RFC) << 8 | T(RC)); in nv50_ram_timing_calc()
115 timing[1] = (T(WR) + 1 + T(CWL)) << 24 | in nv50_ram_timing_calc()
119 timing[2] = (T(CWL) - 1) << 24 | in nv50_ram_timing_calc()
123 timing[3] = (unkt3b - 2 + T(CL)) << 24 | in nv50_ram_timing_calc()
127 timing[4] = (cur4 & 0xffff0000) | in nv50_ram_timing_calc()
130 timing[5] = T(RFC) << 24 | in nv50_ram_timing_calc()
134 timing[7] = (cur7 & 0xff00ffff) | (T(CL) - 1) << 16; in nv50_ram_timing_calc()
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H A Dnouveau_nvkm_subdev_fb_ramgt215.c353 gt215_ram_timing_calc(struct gt215_ram *ram, u32 *timing) in gt215_ram_timing_calc() argument
379 timing[0] = (T(RP) << 24 | T(RAS) << 16 | T(RFC) << 8 | T(RC)); in gt215_ram_timing_calc()
380 timing[1] = (T(WR) + 1 + T(CWL)) << 24 | in gt215_ram_timing_calc()
384 timing[2] = (T(CWL) - 1) << 24 | in gt215_ram_timing_calc()
388 timing[3] = (cur3 & 0x00ff0000) | in gt215_ram_timing_calc()
392 timing[4] = T(20) << 24 | in gt215_ram_timing_calc()
396 timing[5] = T(RFC) << 24 | in gt215_ram_timing_calc()
400 timing[6] = (0x5a + T(CL)) << 16 | in gt215_ram_timing_calc()
403 timing[7] = (cur7 & 0xff000000) | in gt215_ram_timing_calc()
406 timing[8] = cur8 & 0xffffff00; in gt215_ram_timing_calc()
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/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dsc/
H A Damdgpu_dc_dsc.c41 const struct dc_crtc_timing *timing) in dc_dsc_bandwidth_in_kbps_from_timing() argument
46 if (timing->flags.DSC) { in dc_dsc_bandwidth_in_kbps_from_timing()
47 kbps = (timing->pix_clk_100hz * timing->dsc_cfg.bits_per_pixel); in dc_dsc_bandwidth_in_kbps_from_timing()
52 switch (timing->display_color_depth) { in dc_dsc_bandwidth_in_kbps_from_timing()
77 kbps = timing->pix_clk_100hz / 10; in dc_dsc_bandwidth_in_kbps_from_timing()
80 if (timing->flags.Y_ONLY != 1) { in dc_dsc_bandwidth_in_kbps_from_timing()
83 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) in dc_dsc_bandwidth_in_kbps_from_timing()
85 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) in dc_dsc_bandwidth_in_kbps_from_timing()
339 const struct dc_crtc_timing *timing, in get_dsc_bandwidth_range() argument
343 range->stream_kbps = dc_dsc_bandwidth_in_kbps_from_timing(timing); in get_dsc_bandwidth_range()
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/netbsd-src/sys/arch/arm/fdt/
H A Dplfb_fdt.c255 plfb_get_panel_timing(struct plfb_softc *sc, struct display_timing *timing) in plfb_get_panel_timing() argument
266 return display_timing_parse(panel_timing, timing); in plfb_get_panel_timing()
273 struct display_timing timing; in plfb_init() local
275 if (plfb_get_panel_timing(sc, &timing) != 0) { in plfb_init()
277 timing.hactive = 800; in plfb_init()
278 timing.hback_porch = 128; in plfb_init()
279 timing.hfront_porch = 24; in plfb_init()
280 timing.hsync_len = 72; in plfb_init()
281 timing.vactive = 600; in plfb_init()
282 timing.vback_porch = 22; in plfb_init()
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/netbsd-src/sys/dev/fdt/
H A Ddisplay_timing.c45 display_timing_parse(int phandle, struct display_timing *timing) in display_timing_parse() argument
47 if (GETPROP("clock-frequency", &timing->clock_freq) || in display_timing_parse()
48 GETPROP("hactive", &timing->hactive) || in display_timing_parse()
49 GETPROP("vactive", &timing->vactive) || in display_timing_parse()
50 GETPROP("hfront-porch", &timing->hfront_porch) || in display_timing_parse()
51 GETPROP("hback-porch", &timing->hback_porch) || in display_timing_parse()
52 GETPROP("hsync-len", &timing->hsync_len) || in display_timing_parse()
53 GETPROP("vfront-porch", &timing->vfront_porch) || in display_timing_parse()
54 GETPROP("vback-porch", &timing->vback_porch) || in display_timing_parse()
55 GETPROP("vsync-len", &timing->vsync_len)) in display_timing_parse()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/
H A Damdgpu_dce110_timing_generator_v.c249 const struct dc_crtc_timing *timing) in dce110_timing_generator_v_program_blanking() argument
251 uint32_t vsync_offset = timing->v_border_bottom + in dce110_timing_generator_v_program_blanking()
252 timing->v_front_porch; in dce110_timing_generator_v_program_blanking()
253 uint32_t v_sync_start = timing->v_addressable + vsync_offset; in dce110_timing_generator_v_program_blanking()
255 uint32_t hsync_offset = timing->h_border_right + in dce110_timing_generator_v_program_blanking()
256 timing->h_front_porch; in dce110_timing_generator_v_program_blanking()
257 uint32_t h_sync_start = timing->h_addressable + hsync_offset; in dce110_timing_generator_v_program_blanking()
268 timing->h_total - 1, in dce110_timing_generator_v_program_blanking()
277 timing->v_total - 1, in dce110_timing_generator_v_program_blanking()
285 tmp = timing->h_total - in dce110_timing_generator_v_program_blanking()
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H A Damdgpu_dce110_timing_generator.c72 struct dc_crtc_timing *timing) in dce110_timing_generator_apply_front_porch_workaround() argument
74 if (timing->flags.INTERLACE == 1) { in dce110_timing_generator_apply_front_porch_workaround()
75 if (timing->v_front_porch < 2) in dce110_timing_generator_apply_front_porch_workaround()
76 timing->v_front_porch = 2; in dce110_timing_generator_apply_front_porch_workaround()
78 if (timing->v_front_porch < 1) in dce110_timing_generator_apply_front_porch_workaround()
79 timing->v_front_porch = 1; in dce110_timing_generator_apply_front_porch_workaround()
262 const struct dc_crtc_timing *timing) in program_horz_count_by_2() argument
273 if (timing->flags.HORZ_COUNT_BY_TWO) in program_horz_count_by_2()
608 const struct dc_crtc_timing *timing) in dce110_timing_generator_program_blanking() argument
610 uint32_t vsync_offset = timing->v_border_bottom + in dce110_timing_generator_program_blanking()
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/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/
H A Damdgpu_dce120_timing_generator.c108 const struct dc_crtc_timing *timing, in dce120_timing_generator_validate_timing() argument
111 uint32_t interlace_factor = timing->flags.INTERLACE ? 2 : 1; in dce120_timing_generator_validate_timing()
113 (timing->v_total - timing->v_addressable - in dce120_timing_generator_validate_timing()
114 timing->v_border_top - timing->v_border_bottom) * in dce120_timing_generator_validate_timing()
120 timing, in dce120_timing_generator_validate_timing()
126 timing->h_sync_width < tg110->min_h_sync_width || in dce120_timing_generator_validate_timing()
127 timing->v_sync_width < tg110->min_v_sync_width) in dce120_timing_generator_validate_timing()
134 const struct dc_crtc_timing *timing) in dce120_tg_validate_timing() argument
136 return dce120_timing_generator_validate_timing(tg, timing, SIGNAL_TYPE_NONE); in dce120_tg_validate_timing()
435 const struct dc_crtc_timing *timing) in dce120_timing_generator_program_blanking() argument
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/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
H A Damdgpu_dcn10_optc.c54 static void apply_front_porch_workaround(struct dc_crtc_timing *timing) in apply_front_porch_workaround() argument
56 if (timing->flags.INTERLACE == 1) { in apply_front_porch_workaround()
57 if (timing->v_front_porch < 2) in apply_front_porch_workaround()
58 timing->v_front_porch = 2; in apply_front_porch_workaround()
60 if (timing->v_front_porch < 1) in apply_front_porch_workaround()
61 timing->v_front_porch = 1; in apply_front_porch_workaround()
516 const struct dc_crtc_timing *timing) in optc1_validate_timing() argument
523 ASSERT(timing != NULL); in optc1_validate_timing()
525 v_blank = (timing->v_total - timing->v_addressable - in optc1_validate_timing()
526 timing->v_border_top - timing->v_border_bottom); in optc1_validate_timing()
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H A Damdgpu_dcn10_opp.c315 const struct dc_crtc_timing *timing) in opp1_program_stereo() argument
319 uint32_t active_width = timing->h_addressable - timing->h_border_right - timing->h_border_right; in opp1_program_stereo()
320 uint32_t space1_size = timing->v_total - timing->v_addressable; in opp1_program_stereo()
322 uint32_t space2_size = timing->v_total - timing->v_addressable; in opp1_program_stereo()
340 if (timing->timing_3d_format == TIMING_3D_FORMAT_FRAME_ALTERNATE) in opp1_program_stereo()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/modules/freesync/
H A Damdgpu_freesync.c120 * 10000) * stream->timing.h_total, in calc_duration_in_us_from_v_total()
121 stream->timing.pix_clk_100hz)); in calc_duration_in_us_from_v_total()
138 frame_duration_in_ns) * (stream->timing.pix_clk_100hz / 10)), in calc_v_total_from_refresh()
139 stream->timing.h_total), 1000000); in calc_v_total_from_refresh()
142 if (v_total < stream->timing.v_total) { in calc_v_total_from_refresh()
143 ASSERT(v_total < stream->timing.v_total); in calc_v_total_from_refresh()
144 v_total = stream->timing.v_total; in calc_v_total_from_refresh()
164 duration_in_us) * (stream->timing.pix_clk_100hz / 10)), in calc_v_total_from_duration()
165 stream->timing.h_total), 1000); in calc_v_total_from_duration()
168 if (v_total < stream->timing.v_total) { in calc_v_total_from_duration()
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/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/
H A Damdgpu_dc_link_hwss.c122 pipes[i].stream->timing.pix_clk_100hz; in dp_enable_link_phy()
433 …dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.… in dp_set_dsc_on_stream()
434 …dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v… in dp_set_dsc_on_stream()
435 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; in dp_set_dsc_on_stream()
436 dsc_cfg.color_depth = stream->timing.display_color_depth; in dp_set_dsc_on_stream()
437 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; in dp_set_dsc_on_stream()
501 if (!pipe_ctx->stream->timing.flags.DSC) in dp_set_dsc_enable()
526 if (!pipe_ctx->stream->timing.flags.DSC || !dsc) in dp_set_dsc_pps_sdp()
537 …dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h… in dp_set_dsc_pps_sdp()
538 …dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v… in dp_set_dsc_pps_sdp()
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H A Damdgpu_dc_stream.c56 (stream->timing.pix_clk_100hz / 10) > TMDS_MAX_PIXEL_CLOCK && in update_stream_signal()
112 stream->timing.flags.LTE_340MCSC_SCRAMBLE = dc_sink_data->edid_caps.lte_340mcsc_scramble; in dc_stream_construct()
114 memset(&stream->timing.dsc_cfg, 0, sizeof(stream->timing.dsc_cfg)); in dc_stream_construct()
115 stream->timing.dsc_cfg.num_slices_h = 0; in dc_stream_construct()
116 stream->timing.dsc_cfg.num_slices_v = 0; in dc_stream_construct()
117 stream->timing.dsc_cfg.bits_per_pixel = 128; in dc_stream_construct()
118 stream->timing.dsc_cfg.block_pred_enable = 1; in dc_stream_construct()
119 stream->timing.dsc_cfg.linebuf_depth = 9; in dc_stream_construct()
120 stream->timing.dsc_cfg.version_minor = 2; in dc_stream_construct()
121 stream->timing.dsc_cfg.ycbcr422_simple = 0; in dc_stream_construct()
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H A Damdgpu_dc_link.c2079 bool is_vga_mode = (stream->timing.h_addressable == 640) in enable_link_hdmi()
2080 && (stream->timing.v_addressable == 480); in enable_link_hdmi()
2083 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10; in enable_link_hdmi()
2111 stream->timing.flags.LTE_340MCSC_SCRAMBLE); in enable_link_hdmi()
2116 display_color_depth = stream->timing.display_color_depth; in enable_link_hdmi()
2117 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) in enable_link_hdmi()
2137 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10; in enable_link_lvds()
2202 static uint32_t get_timing_pixel_clock_100hz(const struct dc_crtc_timing *timing) in get_timing_pixel_clock_100hz() argument
2205 uint32_t pxl_clk = timing->pix_clk_100hz; in get_timing_pixel_clock_100hz()
2207 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) in get_timing_pixel_clock_100hz()
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H A Damdgpu_dc_resource.c371 if (stream1->timing.h_total != stream2->timing.h_total) in resource_are_streams_timing_synchronizable()
374 if (stream1->timing.v_total != stream2->timing.v_total) in resource_are_streams_timing_synchronizable()
377 if (stream1->timing.h_addressable in resource_are_streams_timing_synchronizable()
378 != stream2->timing.h_addressable) in resource_are_streams_timing_synchronizable()
381 if (stream1->timing.v_addressable in resource_are_streams_timing_synchronizable()
382 != stream2->timing.v_addressable) in resource_are_streams_timing_synchronizable()
385 if (stream1->timing.pix_clk_100hz in resource_are_streams_timing_synchronizable()
386 != stream2->timing.pix_clk_100hz) in resource_are_streams_timing_synchronizable()
971 int store_h_border_left = pipe_ctx->stream->timing.h_border_left; in shift_border_left_to_dst()
974 pipe_ctx->stream->timing.h_border_left = 0; in shift_border_left_to_dst()
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/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce110/
H A Damdgpu_dce110_clk_mgr.c106 uint32_t vertical_total_min = stream->timing.v_total; in dce110_get_min_vblank_time_us()
111 vertical_blank_in_pixels = stream->timing.h_total * in dce110_get_min_vblank_time_us()
113 - stream->timing.v_addressable); in dce110_get_min_vblank_time_us()
115 * 10000 / stream->timing.pix_clk_100hz; in dce110_get_min_vblank_time_us()
168 cfg->v_refresh = stream->timing.pix_clk_100hz * 100; in dce110_fill_display_configs()
169 cfg->v_refresh /= stream->timing.h_total; in dce110_fill_display_configs()
170 cfg->v_refresh = (cfg->v_refresh + stream->timing.v_total / 2) in dce110_fill_display_configs()
171 / stream->timing.v_total; in dce110_fill_display_configs()
241 const struct dc_crtc_timing *timing = in dce11_pplib_apply_display_requirements() local
242 &context->streams[0]->timing; in dce11_pplib_apply_display_requirements()
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/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/modules/info_packet/
H A Damdgpu_info_packet.c152 …if (stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE && stream->view_format != VIEW_3D_FOR… in mod_build_vsc_infopacket()
232 switch (stream->timing.timing_3d_format) { in mod_build_vsc_infopacket()
332 switch (stream->timing.pixel_encoding) { in mod_build_vsc_infopacket()
351 switch (stream->timing.pixel_encoding) { in mod_build_vsc_infopacket()
387 switch (stream->timing.display_color_depth) { in mod_build_vsc_infopacket()
454 format = stream->timing.timing_3d_format; in mod_build_hf_vsif_infopacket()
458 if (stream->timing.hdmi_vic != 0 in mod_build_hf_vsif_infopacket()
459 && stream->timing.h_total >= 3840 in mod_build_hf_vsif_infopacket()
460 && stream->timing.v_total >= 2160 in mod_build_hf_vsif_infopacket()
506 info_packet->sb[5] = stream->timing.hdmi_vic; in mod_build_hf_vsif_infopacket()
/netbsd-src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
H A Dtegra124-nyan-blaze-emc.dtsi7 timing-12750000 {
13 timing-20400000 {
19 timing-40800000 {
25 timing-68000000 {
31 timing-102000000 {
37 timing-204000000 {
43 timing-300000000 {
49 timing-396000000 {
56 timing-600000000 {
62 timing-792000000 {
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H A Dtegra124-jetson-tk1-emc.dtsi7 timing-12750000 {
13 timing-20400000 {
19 timing-40800000 {
25 timing-68000000 {
31 timing-102000000 {
37 timing-204000000 {
43 timing-300000000 {
49 timing-396000000 {
55 timing-528000000 {
61 timing-600000000 {
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H A Dtegra124-apalis-emc.dtsi12 timing-12750000 {
18 timing-20400000 {
24 timing-40800000 {
30 timing-68000000 {
36 timing-102000000 {
42 timing-204000000 {
48 timing-300000000 {
54 timing-396000000 {
60 timing-528000000 {
66 timing-600000000 {
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/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce80/
H A Damdgpu_dce80_timing_generator.c114 const struct dc_crtc_timing *timing, in program_timing() argument
123 program_pix_dur(tg, timing->pix_clk_100hz); in program_timing()
125 dce110_tg_program_timing(tg, timing, 0, 0, 0, 0, 0, use_vbios); in program_timing()
131 const struct dc_crtc_timing *timing) in dce80_timing_generator_enable_advanced_request() argument
151 if ((timing->v_sync_width + timing->v_front_porch) <= 3) { in dce80_timing_generator_enable_advanced_request()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/
H A Damdgpu_dcn_calcs.c413 input->dest.vactive = pipe->stream->timing.v_addressable + pipe->stream->timing.v_border_top in pipe_ctx_to_e2e_pipe_params()
414 + pipe->stream->timing.v_border_bottom; in pipe_ctx_to_e2e_pipe_params()
422 input->dest.htotal = pipe->stream->timing.h_total; in pipe_ctx_to_e2e_pipe_params()
423 input->dest.hblank_start = input->dest.htotal - pipe->stream->timing.h_front_porch; in pipe_ctx_to_e2e_pipe_params()
425 - pipe->stream->timing.h_addressable in pipe_ctx_to_e2e_pipe_params()
426 - pipe->stream->timing.h_border_left in pipe_ctx_to_e2e_pipe_params()
427 - pipe->stream->timing.h_border_right; in pipe_ctx_to_e2e_pipe_params()
429 input->dest.vtotal = pipe->stream->timing.v_total; in pipe_ctx_to_e2e_pipe_params()
430 input->dest.vblank_start = input->dest.vtotal - pipe->stream->timing.v_front_porch; in pipe_ctx_to_e2e_pipe_params()
432 - pipe->stream->timing.v_addressable in pipe_ctx_to_e2e_pipe_params()
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/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_mst_types.c523 struct dc_crtc_timing *timing; member
552 memset(&params[i].timing->dsc_cfg, 0, sizeof(params[i].timing->dsc_cfg)); in set_dsc_configs_from_fairness_vars()
558 params[i].timing, in set_dsc_configs_from_fairness_vars()
559 &params[i].timing->dsc_cfg)) { in set_dsc_configs_from_fairness_vars()
560 params[i].timing->flags.DSC = 1; in set_dsc_configs_from_fairness_vars()
561 params[i].timing->dsc_cfg.bits_per_pixel = vars[i].bpp_x16; in set_dsc_configs_from_fairness_vars()
563 params[i].timing->flags.DSC = 0; in set_dsc_configs_from_fairness_vars()
578 (int) kbps, param.timing, &dsc_config); in bpp_x16_from_pbn()
767 stream->timing.flags.DSC = 0; in compute_mst_dsc_configs_for_link()
769 params[count].timing = &stream->timing; in compute_mst_dsc_configs_for_link()
[all …]
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
H A Damdgpu_dcn20_optc.c215 bool optc2_is_two_pixels_per_containter(const struct dc_crtc_timing *timing) in optc2_is_two_pixels_per_containter() argument
217 return optc1_is_two_pixels_per_containter(timing); in optc2_is_two_pixels_per_containter()
241 struct dc_crtc_timing *timing) in optc2_set_odm_combine() argument
244 int mpcc_hactive = (timing->h_addressable + timing->h_border_left + timing->h_border_right) in optc2_set_odm_combine()
270 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) in optc2_set_odm_combine()
272 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) in optc2_set_odm_combine()

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