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Searched refs:tg_inst (Results 1 – 8 of 8) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
H A Damdgpu_dce_hwseq.c173 unsigned int tg_inst) in dce_crtc_switch_to_clk_src() argument
176 REG_UPDATE(PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
182 REG_UPDATE_2(PHYPLL_PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
186 REG_UPDATE(PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
192 REG_UPDATE_2(PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
196 if (REG(PHYPLL_PIXEL_RATE_CNTL[tg_inst])) in dce_crtc_switch_to_clk_src()
197 REG_UPDATE(PHYPLL_PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
201 clk_src->id, tg_inst); in dce_crtc_switch_to_clk_src()
H A Damdgpu_dce_stream_encoder.c1595 int tg_inst, bool enable) in setup_stereo_sync() argument
1598 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst); in setup_stereo_sync()
1604 int tg_inst) in dig_connect_to_otg() argument
1608 REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst); in dig_connect_to_otg()
1614 uint32_t tg_inst = 0; in dig_source_otg() local
1617 REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst); in dig_source_otg()
1619 return tg_inst; in dig_source_otg()
H A Ddce_hwseq.h835 unsigned int tg_inst);
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/
H A Dstream_encoder.h198 int tg_inst,
206 int tg_inst);
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
H A Damdgpu_dcn10_stream_encoder.c1532 int tg_inst, bool enable) in enc1_setup_stereo_sync() argument
1535 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst); in enc1_setup_stereo_sync()
1541 int tg_inst) in enc1_dig_connect_to_otg() argument
1545 REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst); in enc1_dig_connect_to_otg()
1551 uint32_t tg_inst = 0; in enc1_dig_source_otg() local
1554 REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst); in enc1_dig_source_otg()
1556 return tg_inst; in enc1_dig_source_otg()
H A Ddcn10_stream_encoder.h562 int tg_inst, bool enable);
594 int tg_inst);
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/
H A Damdgpu_dc_resource.c1888 unsigned int i, inst, tg_inst = 0; in acquire_resource_from_hw_enabled_state() local
1901 tg_inst = pool->stream_enc[i]->funcs->dig_source_otg( in acquire_resource_from_hw_enabled_state()
1911 if (tg_inst >= pool->timing_generator_count) in acquire_resource_from_hw_enabled_state()
1914 if (!res_ctx->pipe_ctx[tg_inst].stream) { in acquire_resource_from_hw_enabled_state()
1915 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[tg_inst]; in acquire_resource_from_hw_enabled_state()
1917 pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst]; in acquire_resource_from_hw_enabled_state()
1918 pipe_ctx->plane_res.mi = pool->mis[tg_inst]; in acquire_resource_from_hw_enabled_state()
1919 pipe_ctx->plane_res.hubp = pool->hubps[tg_inst]; in acquire_resource_from_hw_enabled_state()
1920 pipe_ctx->plane_res.ipp = pool->ipps[tg_inst]; in acquire_resource_from_hw_enabled_state()
1921 pipe_ctx->plane_res.xfm = pool->transforms[tg_inst]; in acquire_resource_from_hw_enabled_state()
[all …]
H A Damdgpu_dc.c1055 unsigned int i, enc_inst, tg_inst = 0; in dc_validate_seamless_boot_timing() local
1076 tg_inst = dc->res_pool->stream_enc[i]->funcs->dig_source_otg( in dc_validate_seamless_boot_timing()
1086 if (tg_inst >= dc->res_pool->timing_generator_count) in dc_validate_seamless_boot_timing()
1089 tg = dc->res_pool->timing_generators[tg_inst]; in dc_validate_seamless_boot_timing()
1138 tg_inst, &pix_clk_100hz); in dc_validate_seamless_boot_timing()