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Searched refs:sub5 (Results 1 – 5 of 5) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DR600RegisterInfo.cpp27 R600::sub4, R600::sub5, R600::sub6, R600::sub7, in getSubRegFromChannel()
H A DSIRegisterInfo.td60 list<SubRegIndex> ret6 = [sub0, sub1, sub2, sub3, sub4, sub5];
61 list<SubRegIndex> ret8 = [sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7];
63 sub4, sub5, sub6, sub7,
67 sub4, sub5, sub6, sub7,
H A DSIInstrInfo.cpp2577 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, in insertSelect()
/netbsd-src/external/gpl3/binutils.old/dist/include/opcode/
H A Dnds32.h63 #define N32_TYPE4(op6, rt5, ra5, rb5, rd5, sub5) \ argument
66 | __MF (rd5, 5, 5) | __MF (sub5, 0, 5))
/netbsd-src/external/gpl3/binutils/dist/include/opcode/
H A Dnds32.h63 #define N32_TYPE4(op6, rt5, ra5, rb5, rd5, sub5) \ argument
66 | __MF (rd5, 5, 5) | __MF (sub5, 0, 5))