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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86InstrAMX.td58 TILE:$src4), []>;
99 let Constraints = "$src4 = $dst" in {
101 GR16:$src2, GR16:$src3, TILE:$src4,
105 GR16:$src3, TILE:$src4, TILE:$src5, TILE:$src6))]>;
107 GR16:$src2, GR16:$src3, TILE:$src4,
111 GR16:$src3, TILE:$src4, TILE:$src5, TILE:$src6))]>;
113 GR16:$src2, GR16:$src3, TILE:$src4,
117 GR16:$src3, TILE:$src4, TILE:$src5, TILE:$src6))]>;
119 GR16:$src2, GR16:$src3, TILE:$src4,
123 GR16:$src3, TILE:$src4, TILE:$src5, TILE:$src6))]>;
[all …]
H A DX86InstrXOP.td421 (ins RC:$src1, RC:$src2, RC:$src3, u4imm:$src4),
423 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
425 (VT (X86vpermil2 RC:$src1, RC:$src2, RC:$src3, (i8 timm:$src4))))]>,
428 (ins RC:$src1, RC:$src2, intmemop:$src3, u4imm:$src4),
430 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
433 (i8 timm:$src4))))]>, VEX_W,
436 (ins RC:$src1, fpmemop:$src2, RC:$src3, u4imm:$src4),
438 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
441 RC:$src3, (i8 timm:$src4))))]>,
450 (ins RC:$src1, RC:$src2, RC:$src3, u4imm:$src4),
[all …]
H A DX86InstrAVX512.td11115 (ins _.RC:$src2, _.RC:$src3, u8imm:$src4),
11116 OpcodeStr, "$src4, $src3, $src2", "$src2, $src3, $src4",
11120 (i8 timm:$src4)), 1, 1>,
11123 (ins _.RC:$src2, _.MemOp:$src3, u8imm:$src4),
11124 OpcodeStr, "$src4, $src3, $src2", "$src2, $src3, $src4",
11128 (i8 timm:$src4)), 1, 0>,
11132 (ins _.RC:$src2, _.ScalarMemOp:$src3, u8imm:$src4),
11133 OpcodeStr, "$src4, ${src3}"#_.BroadcastStr#", $src2",
11134 "$src2, ${src3}"#_.BroadcastStr#", $src4",
11138 (i8 timm:$src4)), 1, 0>, EVEX_B,
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonMapAsm2IntrinV62.gen.td114 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4),
115 (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4)>;
117 HvxVR:$src3, imm:$src4),
118 (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4)>;
122 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4),
123 (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4)>;
125 HvxVR:$src3, imm:$src4),
126 (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4)>;
H A DHexagonIntrinsicsV60.td271 def: Pat<(IntID HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, imm:$src4),
272 (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, imm:$src4)>;
275 IntRegs:$src3, imm:$src4),
276 (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, imm:$src4)>;
280 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4),
281 (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4)>;
284 HvxVR:$src3, IntRegs:$src4),
285 (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4)>;
289 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4),
290 (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4)>;
[all …]
H A DHexagonDepMapAsm2Intrin.td612 def: Pat<(int_hexagon_F2_sffma_sc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3, PredRegs:$src4),
613 …(F2_sffma_sc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3, (C2_tfrrp PredRegs:$src4))>, Requires<[H…
1418 …nt_hexagon_S2_insert IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3, u5_0ImmPred_timm:$src4),
1419 …(S2_insert IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3, u5_0ImmPred_timm:$src4)>, Require…
1422 …gon_S2_insertp DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3, u6_0ImmPred_timm:$src4),
1423 …leRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3, u6_0ImmPred_timm:$src4)>, Requires<[HasV5]…
1642 …exagon_S4_vrcrotate_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3, u2_0ImmPred_timm:$src4),
1643 …_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3, u2_0ImmPred_timm:$src4)>, Requires<[HasV5]…
2419 def: Pat<(int_hexagon_V6_vlutvvb_oracc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4),
2420 …(V6_vlutvvb_oracc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4)>, Requires<[HasV60, Us…
[all …]
H A DHexagonIntrinsicsV5.td184 IntRegs:$src3, u2_0ImmPred:$src4),
186 IntRegs:$src3, u2_0ImmPred:$src4)>;
H A DHexagonIntrinsics.td145 : Pat <(IntID I32:$src1, I32:$src2, u4_0ImmPred_timm:$src3, u5_0ImmPred_timm:$src4),
147 (XformImm u5_0ImmPred:$src4))>;
/netbsd-src/sys/netinet/
H A Dudp_usrreq.c488 struct in_addr *src4, *dst4; in udp4_realinput() local
498 src4 = &src->sin_addr; in udp4_realinput()
539 if (!in_hosteq(in4p_faddr(inp), *src4) || in udp4_realinput()
564 inp = inpcb_lookup(&udbtable, *src4, *sport, *dst4, in udp4_realinput()
/netbsd-src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
H A Dr8a7745-iwg22d-sodimm.dts293 capture = <&ssi4>, <&src4>, <&dvc1>;
H A Dr8a7778.dtsi283 src4: src-4 { }; label
662 "sru-src3", "sru-src4", "sru-src5",
H A Dr8a7742-iwg21d-q7.dts390 playback = <&ssi4>, <&src4>, <&dvc1>;
H A Dr8a7794.dtsi1055 src4: src-4 { label
H A Dr8a7793.dtsi1073 src4: src-4 { label
H A Dr8a7745.dtsi1219 src4: src-4 { label
H A Dr8a7790.dtsi1214 src4: src-4 { label
H A Dr8a7791.dtsi1327 src4: src-4 { label
H A Dr8a7744.dtsi1289 src4: src-4 { label
H A Dr8a7742.dtsi1261 src4: src-4 { label
H A Dr8a7743.dtsi1289 src4: src-4 { label
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.td2518 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2522 "\t[$addr], {{$src1, $src2, $src3, $src4}};", []>;
2525 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2529 "\t[$addr], {{$src1, $src2, $src3, $src4}};", []>;
2532 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2536 "\t[$addr], {{$src1, $src2, $src3, $src4}};", []>;
2539 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2543 "\t[$addr+$offset], {{$src1, $src2, $src3, $src4}};", []>;
2546 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2550 "\t[$addr+$offset], {{$src1, $src2, $src3, $src4}};", []>;
[all …]
/netbsd-src/external/gpl3/gdb/dist/sim/testsuite/sh/
H A Dmovxy.s11 src4: .word 4 label
176 srcp4: .long src4
267 srcp4b: .long src4
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.td528 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3, GRRegs:$src4),
529 "lmul $dst1, $dst2, $src1, $src2, $src3, $src4", []>;
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMInstrNEON.td1270 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
1273 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []>,
1312 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
1315 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb",
2032 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
2033 IIC_VST4, "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
2052 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST4u,
2053 "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
2350 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4,
2352 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn",
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DBUFInstructions.td1429 …(ops node:$src0, node:$src1, node:$src2, node:$src3, node:$src4, node:$src5, node:$src6, node:$src…
1430 (vt (Op $src0, $src1, $src2, $src3, $src4, $src5, $src6, $src7)),

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