Home
last modified time | relevance | path

Searched refs:src1 (Results 1 – 25 of 342) sorted by relevance

12345678910>>...14

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonDepMapAsm2Intrin.td14 def: Pat<(int_hexagon_A2_abs IntRegs:$src1),
15 (A2_abs IntRegs:$src1)>, Requires<[HasV5]>;
16 def: Pat<(int_hexagon_A2_absp DoubleRegs:$src1),
17 (A2_absp DoubleRegs:$src1)>, Requires<[HasV5]>;
18 def: Pat<(int_hexagon_A2_abssat IntRegs:$src1),
19 (A2_abssat IntRegs:$src1)>, Requires<[HasV5]>;
20 def: Pat<(int_hexagon_A2_add IntRegs:$src1, IntRegs:$src2),
21 (A2_add IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;
22 def: Pat<(int_hexagon_A2_addh_h16_hh IntRegs:$src1, IntRegs:$src2),
23 (A2_addh_h16_hh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;
[all …]
H A DHexagonMapAsm2IntrinV62.gen.td10 def: Pat<(IntID HvxVR:$src1, IntRegs:$src2),
11 (MI HvxVR:$src1, IntRegs:$src2)>;
12 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, IntRegs:$src2),
13 (MI HvxVR:$src1, IntRegs:$src2)>;
17 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),
18 (MI HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>;
19 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
21 (MI HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>;
25 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2),
26 (MI HvxVR:$src1, HvxVR:$src2)>;
[all …]
H A DHexagonIntrinsicsV60.td15 def : Pat < (v16i32 (int_hexagon_V6_lo (v32i32 HvxWR:$src1))),
16 (v16i32 (EXTRACT_SUBREG (v32i32 HvxWR:$src1), vsub_lo)) >;
18 def : Pat < (v16i32 (int_hexagon_V6_hi (v32i32 HvxWR:$src1))),
19 (v16i32 (EXTRACT_SUBREG (v32i32 HvxWR:$src1), vsub_hi)) >;
21 def : Pat < (v32i32 (int_hexagon_V6_lo_128B (v64i32 HvxWR:$src1))),
22 (v32i32 (EXTRACT_SUBREG (v64i32 HvxWR:$src1), vsub_lo)) >;
24 def : Pat < (v32i32 (int_hexagon_V6_hi_128B (v64i32 HvxWR:$src1))),
25 (v32i32 (EXTRACT_SUBREG (v64i32 HvxWR:$src1), vsub_hi)) >;
28 def : Pat <(v64i1 (bitconvert (v16i32 HvxVR:$src1))),
29 (v64i1 (V6_vandvrt(v16i32 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
[all …]
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/c6x/
H A Dc6x_intrinsics.h58 _sadd (int src1, int src2) in _sadd() argument
60 return __builtin_c6x_sadd (src1, src2); in _sadd()
64 _ssub (int src1, int src2) in _ssub() argument
66 return __builtin_c6x_ssub (src1, src2); in _ssub()
70 _add2 (int src1, int src2) in _add2() argument
72 return (int)__builtin_c6x_add2 ((__v2hi)src1, (__v2hi)src2); in _add2()
76 _sub2 (int src1, int src2) in _sub2() argument
78 return (int)__builtin_c6x_sub2 ((__v2hi)src1, (__v2hi)src2); in _sub2()
82 _add4 (int src1, int src2) in _add4() argument
84 return (int)__builtin_c6x_add4 ((__uv4qi)src1, (__uv4qi)src2); in _add4()
[all …]
/netbsd-src/external/gpl3/gcc/dist/gcc/config/c6x/
H A Dc6x_intrinsics.h58 _sadd (int src1, int src2) in _sadd() argument
60 return __builtin_c6x_sadd (src1, src2); in _sadd()
64 _ssub (int src1, int src2) in _ssub() argument
66 return __builtin_c6x_ssub (src1, src2); in _ssub()
70 _add2 (int src1, int src2) in _add2() argument
72 return (int)__builtin_c6x_add2 ((__v2hi)src1, (__v2hi)src2); in _add2()
76 _sub2 (int src1, int src2) in _sub2() argument
78 return (int)__builtin_c6x_sub2 ((__v2hi)src1, (__v2hi)src2); in _sub2()
82 _add4 (int src1, int src2) in _add4() argument
84 return (int)__builtin_c6x_add4 ((__uv4qi)src1, (__uv4qi)src2); in _add4()
[all …]
/netbsd-src/external/apache2/llvm/dist/clang/lib/Headers/
H A Damxintrin.h151 #define _tile_dpbssd(dst, src0, src1) \ argument
152 __builtin_ia32_tdpbssd((dst), (src0), (src1))
170 #define _tile_dpbsud(dst, src0, src1) \ argument
171 __builtin_ia32_tdpbsud((dst), (src0), (src1))
189 #define _tile_dpbusd(dst, src0, src1) \ argument
190 __builtin_ia32_tdpbusd((dst), (src0), (src1))
208 #define _tile_dpbuud(dst, src0, src1) \ argument
209 __builtin_ia32_tdpbuud((dst), (src0), (src1))
226 #define _tile_dpbf16ps(dst, src0, src1) \ argument
227 __builtin_ia32_tdpbf16ps((dst), (src0), (src1))
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86InstrXOP.td97 (ins VR128:$src1, VR128:$src2),
98 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
100 (vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2))))]>,
103 (ins VR128:$src1, i128mem:$src2),
104 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
106 (vt128 (OpNode (vt128 VR128:$src1),
110 (ins i128mem:$src1, VR128:$src2),
111 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
113 (vt128 (OpNode (vt128 (load addr:$src1)),
119 (ins VR128:$src1, VR128:$src2),
[all …]
H A DX86InstrShiftRotate.td17 let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
19 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1),
21 [(set GR8:$dst, (shl GR8:$src1, CL))]>;
22 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
24 [(set GR16:$dst, (shl GR16:$src1, CL))]>, OpSize16;
25 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
27 [(set GR32:$dst, (shl GR32:$src1, CL))]>, OpSize32;
28 def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
30 [(set GR64:$dst, (shl GR64:$src1, CL))]>;
34 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2),
[all …]
H A DX86InstrSSE.td26 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
29 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
30 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], d>,
33 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
36 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
37 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], d>,
49 def rr_Int : SI_Int<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
52 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
53 [(set RC:$dst, (VT (OpNode RC:$src1, RC:$src2)))], d>,
56 def rm_Int : SI_Int<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
[all …]
H A DX86InstrKL.td21 def LOADIWKEY : I<0xDC, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
22 "loadiwkey\t{$src2, $src1|$src1, $src2}",
23 [(int_x86_loadiwkey XMM0, VR128:$src1, VR128:$src2, EAX)]>, T8XS,
39 let Constraints = "$src1 = $dst",
41 def AESENC128KL : I<0xDC, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, opaquemem:$src2),
42 "aesenc128kl\t{$src2, $src1|$src1, $src2}",
44 (X86aesenc128kl VR128:$src1, addr:$src2))]>, T8XS,
47 def AESDEC128KL : I<0xDD, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, opaquemem:$src2),
48 "aesdec128kl\t{$src2, $src1|$src1, $src2}",
50 (X86aesdec128kl VR128:$src1, addr:$src2))]>, T8XS,
[all …]
H A DX86InstrArithmetic.td149 let Constraints = "$src1 = $dst" in {
154 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
157 (X86smul_flag GR16:$src1, GR16:$src2))]>,
159 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
162 (X86smul_flag GR32:$src1, GR32:$src2))]>,
165 (ins GR64:$src1, GR64:$src2),
168 (X86smul_flag GR64:$src1, GR64:$src2))]>,
174 (ins GR16:$src1, i16mem:$src2),
177 (X86smul_flag GR16:$src1, (loadi16 addr:$src2)))]>,
180 (ins GR32:$src1, i32mem:$src2),
[all …]
H A DX86InstrCompiler.td1014 def : Pat<(op FR32:$src1, (bitconvert (i32 (atomic_load_32 addr:$src2)))),
1015 (!cast<Instruction>(Name#"SSrm") FR32:$src1, addr:$src2)>,
1017 def : Pat<(op FR32:$src1, (bitconvert (i32 (atomic_load_32 addr:$src2)))),
1018 (!cast<Instruction>("V"#Name#"SSrm") FR32:$src1, addr:$src2)>,
1020 def : Pat<(op FR32X:$src1, (bitconvert (i32 (atomic_load_32 addr:$src2)))),
1021 (!cast<Instruction>("V"#Name#"SSZrm") FR32X:$src1, addr:$src2)>,
1024 def : Pat<(op FR64:$src1, (bitconvert (i64 (atomic_load_64 addr:$src2)))),
1025 (!cast<Instruction>(Name#"SDrm") FR64:$src1, addr:$src2)>,
1027 def : Pat<(op FR64:$src1, (bitconvert (i64 (atomic_load_64 addr:$src2)))),
1028 (!cast<Instruction>("V"#Name#"SDrm") FR64:$src1, addr:$src2)>,
[all …]
H A DX86InstrFMA.td40 (ins RC:$src1, RC:$src2, RC:$src3),
43 [(set RC:$dst, (VT (Op RC:$src2, RC:$src1, RC:$src3)))]>,
48 (ins RC:$src1, RC:$src2, x86memop:$src3),
51 [(set RC:$dst, (VT (Op RC:$src2, RC:$src1,
61 (ins RC:$src1, RC:$src2, RC:$src3),
68 (ins RC:$src1, RC:$src2, x86memop:$src3),
72 RC:$src1)))]>,
81 (ins RC:$src1, RC:$src2, RC:$src3),
90 (ins RC:$src1, RC:$src2, x86memop:$src3),
93 [(set RC:$dst, (VT (Op (MemFrag addr:$src3), RC:$src1,
[all …]
H A DX86InstrAMX.td53 def PTILELOADDV : PseudoI<(outs TILE:$dst), (ins GR16:$src1,
56 def PTILESTOREDV : PseudoI<(outs), (ins GR16:$src1,
60 def PTILEZEROV : PseudoI<(outs TILE:$dst), (ins GR16:$src1, GR16:$src2),
62 GR16:$src1, GR16:$src2))]>;
67 def PTILELOADD : PseudoI<(outs), (ins u8imm:$src1, sibmem:$src2), []>;
68 def PTILELOADDT1 : PseudoI<(outs), (ins u8imm:$src1,
79 let Constraints = "$src1 = $dst" in {
81 (ins TILE:$src1, TILE:$src2, TILE:$src3),
85 (ins TILE:$src1, TILE:$src2, TILE:$src3),
89 (ins TILE:$src1, TILE:$src2, TILE:$src3),
[all …]
H A DX86InstrAVX512.td174 def vselect_mask : PatFrag<(ops node:$mask, node:$src1, node:$src2),
175 (vselect node:$mask, node:$src1, node:$src2), [{
179 def X86selects_mask : PatFrag<(ops node:$mask, node:$src1, node:$src2),
180 (X86selects node:$mask, node:$src1, node:$src2), [{
299 // ($src1) is already tied to $dst so we just use that for the preserved
301 // $src1.
311 !con((ins _.RC:$src1), NonTiedIns),
312 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
313 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
316 (Select _.KRCWM:$mask, RHS, _.RC:$src1),
[all …]
/netbsd-src/sys/external/bsd/sljit/dist/sljit_src/
H A DsljitNativePPC_32.c47 sljit_s32 dst, sljit_s32 src1, sljit_s32 src2) in emit_single_op() argument
54 SLJIT_ASSERT(src1 == TMP_REG1); in emit_single_op()
61 SLJIT_ASSERT(src1 == TMP_REG1); in emit_single_op()
76 SLJIT_ASSERT(src1 == TMP_REG1); in emit_single_op()
88 SLJIT_ASSERT(src1 == TMP_REG1); in emit_single_op()
92 SLJIT_ASSERT(src1 == TMP_REG1); in emit_single_op()
96 SLJIT_ASSERT(src1 == TMP_REG1); in emit_single_op()
103 return push_inst(compiler, ADDI | D(dst) | A(src1) | compiler->imm); in emit_single_op()
108 return push_inst(compiler, ADDIS | D(dst) | A(src1) | compiler->imm); in emit_single_op()
112 return push_inst(compiler, ADDIC | D(dst) | A(src1) | compiler->imm); in emit_single_op()
[all …]
H A DsljitNativePPC_64.c135 FAIL_IF(push_inst(compiler, EXTSW | S(src1) | A(TMP_REG1))); \
136 src1 = TMP_REG1; \
146 FAIL_IF(push_inst(compiler, EXTSW | S(src1) | A(TMP_REG1))); \
147 src1 = TMP_REG1; \
151 sljit_s32 dst, sljit_s32 src1, sljit_s32 src2) in emit_single_op() argument
156 SLJIT_ASSERT(src1 == TMP_REG1); in emit_single_op()
163 SLJIT_ASSERT(src1 == TMP_REG1); in emit_single_op()
176 SLJIT_ASSERT(src1 == TMP_REG1); in emit_single_op()
191 SLJIT_ASSERT(src1 == TMP_REG1); in emit_single_op()
203 SLJIT_ASSERT(src1 == TMP_REG1); in emit_single_op()
[all …]
H A DsljitNativeMIPS_32.c46 FAIL_IF(push_inst(compiler, op_imm | S(src1) | TA(EQUAL_FLAG) | IMM(src2), EQUAL_FLAG)); \
48 FAIL_IF(push_inst(compiler, op_imm | S(src1) | T(dst) | IMM(src2), DR(dst))); \
52 FAIL_IF(push_inst(compiler, op_norm | S(src1) | T(src2) | DA(EQUAL_FLAG), EQUAL_FLAG)); \
54 FAIL_IF(push_inst(compiler, op_norm | S(src1) | T(src2) | D(dst), DR(dst))); \
60 FAIL_IF(push_inst(compiler, op_imm | T(src1) | DA(EQUAL_FLAG) | SH_IMM(src2), EQUAL_FLAG)); \
62 FAIL_IF(push_inst(compiler, op_imm | T(src1) | D(dst) | SH_IMM(src2), DR(dst))); \
66 FAIL_IF(push_inst(compiler, op_v | S(src2) | T(src1) | DA(EQUAL_FLAG), EQUAL_FLAG)); \
68 FAIL_IF(push_inst(compiler, op_v | S(src2) | T(src1) | D(dst), DR(dst))); \
72 sljit_s32 dst, sljit_s32 src1, sljit_sw src2) in emit_single_op() argument
81 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & SRC2_IMM)); in emit_single_op()
[all …]
H A DsljitNativeMIPS_64.c129 FAIL_IF(push_inst(compiler, op_imm | S(src1) | TA(EQUAL_FLAG) | IMM(src2), EQUAL_FLAG)); \
131 FAIL_IF(push_inst(compiler, op_imm | S(src1) | T(dst) | IMM(src2), DR(dst))); \
135 FAIL_IF(push_inst(compiler, op_norm | S(src1) | T(src2) | DA(EQUAL_FLAG), EQUAL_FLAG)); \
137 FAIL_IF(push_inst(compiler, op_norm | S(src1) | T(src2) | D(dst), DR(dst))); \
150 FAIL_IF(push_inst(compiler, ins | T(src1) | DA(EQUAL_FLAG) | SH_IMM(src2), EQUAL_FLAG)); \
152 FAIL_IF(push_inst(compiler, ins | T(src1) | D(dst) | SH_IMM(src2), DR(dst))); \
157 FAIL_IF(push_inst(compiler, ins | S(src2) | T(src1) | DA(EQUAL_FLAG), EQUAL_FLAG)); \
159 FAIL_IF(push_inst(compiler, ins | S(src2) | T(src1) | D(dst), DR(dst))); \
163 sljit_s32 dst, sljit_s32 src1, sljit_sw src2) in emit_single_op() argument
171 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & SRC2_IMM)); in emit_single_op()
[all …]
/netbsd-src/external/gpl3/gcc.old/dist/libhsail-rt/rt/
H A Dbitstring.c40 __hsail_bitextract_u32 (uint32_t src0, uint32_t src1, uint32_t src2) in __hsail_bitextract_u32() argument
42 BITEXTRACT (uint32_t, src0, src1, src2); in __hsail_bitextract_u32()
46 __hsail_bitextract_s32 (int32_t src0, uint32_t src1, uint32_t src2) in __hsail_bitextract_s32() argument
48 BITEXTRACT (int32_t, src0, src1, src2); in __hsail_bitextract_s32()
52 __hsail_bitextract_u64 (uint64_t src0, uint32_t src1, uint32_t src2) in __hsail_bitextract_u64() argument
54 BITEXTRACT (uint64_t, src0, src1, src2); in __hsail_bitextract_u64()
58 __hsail_bitextract_s64 (int64_t src0, uint32_t src1, uint32_t src2) in __hsail_bitextract_s64() argument
60 BITEXTRACT (int64_t, src0, src1, src2); in __hsail_bitextract_s64()
70 __hsail_bitinsert_u32 (uint32_t src0, uint32_t src1, uint32_t src2, in __hsail_bitinsert_u32() argument
73 BITINSERT (uint32_t, src0, src1, src2, src3); in __hsail_bitinsert_u32()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstrInfo.td189 // out = (src0 + src1 > 0xFFFFFFFF) ? 1 : 0
192 // out = (src1 > src0) ? 1 : 0
229 // src1 = Denominator, src2 = Numerator).
234 // Special case divide fixup and flags(src0 = Quotient, src1 =
254 // src1: dst - rat offset (aka pointer) in dwords
323 SDTCisSameAs<3, 2>, // f32 src1
387 def AMDGPUldexp : PatFrags<(ops node:$src0, node:$src1),
388 [(int_amdgcn_ldexp node:$src0, node:$src1),
389 (AMDGPUldexp_impl node:$src0, node:$src1)]>;
391 def AMDGPUfp_class : PatFrags<(ops node:$src0, node:$src1),
[all …]
/netbsd-src/external/gpl3/gcc/dist/gcc/config/i386/
H A Damxint8intrin.h38 #define _tile_int8_dp_internal(name,dst,src1,src2) \ argument
40 …("{"#name"\t%%tmm"#src2", %%tmm"#src1", %%tmm"#dst"|"#name"\t%%tmm"#dst", %%tmm"#src1", %%tmm"#src…
42 #define _tile_dpbssd(dst,src1,src2) \ argument
43 _tile_int8_dp_internal (tdpbssd, dst, src1, src2)
45 #define _tile_dpbsud(dst,src1,src2) \ argument
46 _tile_int8_dp_internal (tdpbsud, dst, src1, src2)
48 #define _tile_dpbusd(dst,src1,src2) \ argument
49 _tile_int8_dp_internal (tdpbusd, dst, src1, src2)
51 #define _tile_dpbuud(dst,src1,src2) \ argument
52 _tile_int8_dp_internal (tdpbuud, dst, src1, src2)
/netbsd-src/external/gpl3/binutils/dist/gas/
H A Dscfi.c271 struct ginsn_src *src1; in ginsn_scfi_restore_reg_p() local
274 src1 = ginsn_get_src1 (ginsn); in ginsn_scfi_restore_reg_p()
281 && ginsn_get_src_type (src1) == GINSN_SRC_INDIRECT in ginsn_scfi_restore_reg_p()
282 && (ginsn_get_src_reg (src1) == REG_SP in ginsn_scfi_restore_reg_p()
283 || (ginsn_get_src_reg (src1) == REG_FP in ginsn_scfi_restore_reg_p()
288 && ginsn_get_src_type (src1) == GINSN_SRC_INDIRECT in ginsn_scfi_restore_reg_p()
289 && ginsn_get_src_reg (src1) == REG_SP) in ginsn_scfi_restore_reg_p()
476 struct ginsn_src *src1; in verify_heuristic_traceable_reg_fp() local
479 src1 = ginsn_get_src1 (ginsn); in verify_heuristic_traceable_reg_fp()
499 && ginsn_get_src_reg (src1) == REG_FP in verify_heuristic_traceable_reg_fp()
[all …]
/netbsd-src/external/gpl3/binutils.old/dist/include/opcode/
H A Dtic6x-opcode-table.h138 FIX3(FIX(op, 0x38), FIX(x, 0), FIX(src1, 0)),
151 ENC4(ENC(s, fu, 0), ENC(src2, regpair_msb, 0), ENC(src1, regpair_lsb, 0),
163 ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
168 ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
173 ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
178 ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
183 ENC4(ENC(s, fu, 0), ENC(src1, scst, 0), ENC(src2, reg, 1),
188 ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
193 ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
199 ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1),
[all …]
/netbsd-src/external/gpl3/binutils/dist/include/opcode/
H A Dtic6x-opcode-table.h138 FIX3(FIX(op, 0x38), FIX(x, 0), FIX(src1, 0)),
151 ENC4(ENC(s, fu, 0), ENC(src2, regpair_msb, 0), ENC(src1, regpair_lsb, 0),
163 ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
168 ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
173 ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
178 ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
183 ENC4(ENC(s, fu, 0), ENC(src1, scst, 0), ENC(src2, reg, 1),
188 ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
193 ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
199 ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1),
[all …]

12345678910>>...14