| /netbsd-src/external/gpl3/gcc.old/dist/libhsail-rt/rt/ |
| H A D | bitstring.c | 40 __hsail_bitextract_u32 (uint32_t src0, uint32_t src1, uint32_t src2) in __hsail_bitextract_u32() argument
42 BITEXTRACT (uint32_t, src0, src1, src2); in __hsail_bitextract_u32()
46 __hsail_bitextract_s32 (int32_t src0, uint32_t src1, uint32_t src2) in __hsail_bitextract_s32() argument
48 BITEXTRACT (int32_t, src0, src1, src2); in __hsail_bitextract_s32()
52 __hsail_bitextract_u64 (uint64_t src0, uint32_t src1, uint32_t src2) in __hsail_bitextract_u64() argument
54 BITEXTRACT (uint64_t, src0, src1, src2); in __hsail_bitextract_u64()
58 __hsail_bitextract_s64 (int64_t src0, uint32_t src1, uint32_t src2) in __hsail_bitextract_s64() argument
60 BITEXTRACT (int64_t, src0, src1, src2); in __hsail_bitextract_s64()
70 __hsail_bitinsert_u32 (uint32_t src0, uint32_t src1, uint32_t src2, in __hsail_bitinsert_u32() argument
73 BITINSERT (uint32_t, src0, src1, src2, src3); in __hsail_bitinsert_u32()
[all …]
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| /netbsd-src/external/apache2/llvm/dist/clang/lib/Headers/ |
| H A D | amxintrin.h | 151 #define _tile_dpbssd(dst, src0, src1) \ argument
152 __builtin_ia32_tdpbssd((dst), (src0), (src1))
170 #define _tile_dpbsud(dst, src0, src1) \ argument
171 __builtin_ia32_tdpbsud((dst), (src0), (src1))
189 #define _tile_dpbusd(dst, src0, src1) \ argument
190 __builtin_ia32_tdpbusd((dst), (src0), (src1))
208 #define _tile_dpbuud(dst, src0, src1) \ argument
209 __builtin_ia32_tdpbuud((dst), (src0), (src1))
226 #define _tile_dpbf16ps(dst, src0, src1) \ argument
227 __builtin_ia32_tdpbf16ps((dst), (src0), (src1))
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| /netbsd-src/external/apache2/llvm/dist/llvm/docs/AMDGPU/ |
| H A D | AMDGPUAsmGFX7.rst | 727 …v_add_f32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgp…
728 …mdgpu_synid7_vdst32_0>`, :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32…
729 …mdgpu_synid7_vdst32_0>`, :ref:`vcc<amdgpu_synid7_vcc_64>`, :ref:`src0<amdgpu_synid7_src32…
730 …v_and_b32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgp…
731 …v_ashr_i32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgp…
732 …v_ashrrev_i32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgp…
733 …v_bcnt_u32_b32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgp…
734 …v_bfm_b32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgp…
735 …v_cndmask_b32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgp…
736 …v_cvt_pk_i16_i32 :ref:`vdst<amdgpu_synid7_vdst32_0>`, :ref:`src0<amdgp…
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| H A D | AMDGPUAsmGFX90a.rst | 971 …amdgpu_synid_gfx90a_vdst_14>`, :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a…
973 …amdgpu_synid_gfx90a_vdst_14>`, :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a…
974 …v_add_f16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx9…
976 …v_add_f16_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx9…
977 …v_add_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx9…
979 …v_add_f32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx9…
980 …v_add_u16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx9…
982 …v_add_u16_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx9…
983 …v_add_u32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx9…
985 …v_add_u32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_14>`, :ref:`src0<amdgpu_synid_gfx9…
[all …]
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| H A D | AMDGPUAsmGFX9.rst | 1060 …f:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32…
1062 …f:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32…
1063 …v_add_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`…
1065 …v_add_f16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`…
1066 …v_add_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`…
1068 …v_add_f32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`…
1069 …v_add_u16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`…
1071 …v_add_u16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_1>`…
1072 …v_add_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`…
1074 …v_add_u32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src0<amdgpu_synid9_src32_0>`…
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| H A D | AMDGPUAsmGFX10.rst | 777 …`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src3…
778 …v_add_f16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src3…
779 …v_add_f32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src3…
780 …v_add_nc_u32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src3…
781 …v_and_b32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src3…
782 …v_ashrrev_i32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`src0<amdgpu_synid10_src3…
786 …v_cmp_class_f16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0…
787 …v_cmp_class_f32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0…
788 …v_cmp_eq_f16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0…
789 …v_cmp_eq_f32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0…
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| H A D | AMDGPUAsmGFX8.rst | 876 …v_add_f16 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_0>`…
879 …v_add_f32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_0>`…
882 …v_add_u16 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_1>`…
885 …f:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vcc<amdgpu_synid8_vcc_64>`, :ref:`src0<amdgpu_synid8_src32…
888 …f:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vcc<amdgpu_synid8_vcc_64>`, :ref:`src0<amdgpu_synid8_src32…
891 …v_and_b32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_0>`…
894 …v_ashrrev_i16 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_2>`…
897 …v_ashrrev_i32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_3>`…
900 …v_cndmask_b32 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_0>`…
903 …v_ldexp_f16 :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`src0<amdgpu_synid8_src32_0>`…
[all …]
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| H A D | AMDGPUAsmGFX906.rst | 43 …v_fmac_f32 :ref:`vdst<amdgpu_synid906_vdst32_0>`, :ref:`src0<amdgpu_synid9…
45 …v_xnor_b32 :ref:`vdst<amdgpu_synid906_vdst32_0>`, :ref:`src0<amdgpu_synid9…
47 …v_xnor_b32_sdwa :ref:`vdst<amdgpu_synid906_vdst32_0>`, :ref:`src0<amdgpu_synid9…
56 …v_fmac_f32_e64 :ref:`vdst<amdgpu_synid906_vdst32_0>`, :ref:`src0<amdgpu_synid9…
57 …v_xnor_b32_e64 :ref:`vdst<amdgpu_synid906_vdst32_0>`, :ref:`src0<amdgpu_synid9…
66 …v_dot2_f32_f16 :ref:`vdst<amdgpu_synid906_vdst32_0>`, :ref:`src0<amdgpu_synid9…
67 …v_dot2_i32_i16 :ref:`vdst<amdgpu_synid906_vdst32_0>`, :ref:`src0<amdgpu_synid9…
68 …v_dot2_u32_u16 :ref:`vdst<amdgpu_synid906_vdst32_0>`, :ref:`src0<amdgpu_synid9…
69 …v_dot4_i32_i8 :ref:`vdst<amdgpu_synid906_vdst32_0>`, :ref:`src0<amdgpu_synid9…
70 …v_dot4_u32_u8 :ref:`vdst<amdgpu_synid906_vdst32_0>`, :ref:`src0<amdgpu_synid9…
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| H A D | AMDGPUAsmGFX1011.rst | 63 …v_dot2c_f32_f16 :ref:`vdst<amdgpu_synid1011_vdst32_0>`, :ref:`src0<amdgpu_synid…
64 …v_dot4c_i32_i8 :ref:`vdst<amdgpu_synid1011_vdst32_0>`, :ref:`src0<amdgpu_synid…
73 …v_dot2_f32_f16 :ref:`vdst<amdgpu_synid1011_vdst32_0>`, :ref:`src0<amdgpu_synid…
74 …v_dot2_i32_i16 :ref:`vdst<amdgpu_synid1011_vdst32_0>`, :ref:`src0<amdgpu_synid…
75 …v_dot2_u32_u16 :ref:`vdst<amdgpu_synid1011_vdst32_0>`, :ref:`src0<amdgpu_synid…
76 …v_dot4_i32_i8 :ref:`vdst<amdgpu_synid1011_vdst32_0>`, :ref:`src0<amdgpu_synid…
77 …v_dot4_u32_u8 :ref:`vdst<amdgpu_synid1011_vdst32_0>`, :ref:`src0<amdgpu_synid…
78 …v_dot8_i32_i4 :ref:`vdst<amdgpu_synid1011_vdst32_0>`, :ref:`src0<amdgpu_synid…
79 …v_dot8_u32_u4 :ref:`vdst<amdgpu_synid1011_vdst32_0>`, :ref:`src0<amdgpu_synid…
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| H A D | AMDGPUAsmGFX908.rst | 63 …v_dot2c_f32_f16 :ref:`vdst<amdgpu_synid908_vdst32_0>`, :ref:`src0<amdgpu_synid908_src3…
65 …v_dot2c_i32_i16 :ref:`vdst<amdgpu_synid908_vdst32_0>`, :ref:`src0<amdgpu_synid908_src3…
67 …v_dot4c_i32_i8 :ref:`vdst<amdgpu_synid908_vdst32_0>`, :ref:`src0<amdgpu_synid908_src3…
69 …v_dot8c_i32_i4 :ref:`vdst<amdgpu_synid908_vdst32_0>`, :ref:`src0<amdgpu_synid908_src3…
71 …v_fmac_f32 :ref:`vdst<amdgpu_synid908_vdst32_0>`, :ref:`src0<amdgpu_synid908_src3…
73 …<amdgpu_synid908_vdst32_0>`::ref:`f16x2<amdgpu_synid908_type_dev>`, :ref:`src0<amdgpu_synid908_src…
74 …v_xnor_b32 :ref:`vdst<amdgpu_synid908_vdst32_0>`, :ref:`src0<amdgpu_synid908_src3…
76 …v_xnor_b32_sdwa :ref:`vdst<amdgpu_synid908_vdst32_0>`, :ref:`src0<amdgpu_synid908_src3…
85 …v_fmac_f32_e64 :ref:`vdst<amdgpu_synid908_vdst32_0>`, :ref:`src0<amdgpu_synid9…
86 …v_xnor_b32_e64 :ref:`vdst<amdgpu_synid908_vdst32_0>`, :ref:`src0<amdgpu_synid9…
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstrInfo.td | 189 // out = (src0 + src1 > 0xFFFFFFFF) ? 1 : 0
192 // out = (src1 > src0) ? 1 : 0
228 // Special case divide FMA with scale and flags (src0 = Quotient,
234 // Special case divide fixup and flags(src0 = Quotient, src1 =
253 // src0: vec4(src, 0, 0, mask)
322 // i32 or f32 src0
387 def AMDGPUldexp : PatFrags<(ops node:$src0, node:$src1),
388 [(int_amdgcn_ldexp node:$src0, node:$src1),
389 (AMDGPUldexp_impl node:$src0, node:$src1)]>;
391 def AMDGPUfp_class : PatFrags<(ops node:$src0, node:$src1),
[all …]
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| H A D | SIInstructions.td | 59 let DisableEncoding = "$src0", Constraints = "$src0 = $vdst" in {
64 (ins VGPR_32:$src0, VGPR_32:$vsrc, Attr:$attr, AttrChan:$attrchan),
66 [(set f32:$vdst, (int_amdgcn_interp_p2 f32:$src0, f32:$vsrc,
69 } // End DisableEncoding = "$src0", Constraints = "$src0 = $vdst"
98 (ins VSrc_b64:$src0, VSrc_b64:$src1, SSrc_b64:$src2), "", []> {
107 (ins VSrc_b64:$src0)>;
116 def WQM : PseudoInstSI <(outs unknown:$vdst), (ins unknown:$src0)>;
120 def SOFT_WQM : PseudoInstSI <(outs unknown:$vdst), (ins unknown:$src0)>;
124 // the instruction that defines $src0 (which is run in Whole Wave Mode) doesn't
127 def STRICT_WWM : PseudoInstSI <(outs unknown:$vdst), (ins unknown:$src0)>;
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| H A D | AMDGPUInstructions.td | 161 (ops node:$src0),
162 (op $src0),
171 (ops node:$src0, node:$src1),
172 (op $src0, $src1),
180 (ops node:$src0, node:$src1, node:$src2),
181 (op $src0, $src1, $src2),
189 (ops node:$src0, node:$src1),
190 (op $src0, $src1),
242 (ops node:$src0), (srl_oneuse node:$src0, (i32 16))
247 (ops node:$src0), (i16 (trunc (i32 (srl_16 node:$src0))))
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| H A D | SOPInstructions.td | 73 bits<8> src0;
75 let Inst{7-0} = !if(ps.has_src0, src0, ?);
83 !if(tied_in, (ins SSrc_b32:$src0, SReg_32:$sdst_in),
84 (ins SSrc_b32:$src0)),
85 "$sdst, $src0", pattern> {
91 opName, (outs SReg_32:$sdst), (ins SReg_32:$src0),
92 "$sdst, $src0", pattern>;
96 opName, (outs), (ins SSrc_b32:$src0),
97 "$src0", pattern> {
103 opName, (outs), (ins SReg_32:$sdst, SSrc_b32:$src0),
[all …]
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| H A D | EvergreenInstructions.td | 379 // [(set f64:$dst, (fma f64:$src0, f64:$src1, f64:$src2))]
397 [(set i32:$dst, (AMDGPUbfe_u32 i32:$src0, i32:$src1, i32:$src2))],
402 [(set i32:$dst, (AMDGPUbfe_i32 i32:$src0, i32:$src1, i32:$src2))],
443 [(set i32:$dst, (AMDGPUbfi i32:$src0, i32:$src1, i32:$src2))],
495 (fcopysign f32:$src0, f32:$src1),
496 (BFI_INT_eg (MOV_IMM_I32 (i32 0x7fffffff)), $src0, $src1)
500 (fcopysign f32:$src0, f64:$src1),
501 (BFI_INT_eg (MOV_IMM_I32 (i32 0x7fffffff)), $src0,
506 (fcopysign f64:$src0, f64:$src1),
508 (i32 (EXTRACT_SUBREG $src0, sub0)), sub0,
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| H A D | R600Instructions.td | 107 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
112 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
138 [(set R600_Reg32:$dst, (node R600_Reg32:$src0))], itin
149 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
155 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
177 [(set R600_Reg32:$dst, (node R600_Reg32:$src0,
189 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, SEL:$src0_sel,
195 "$src0_neg$src0$src0_rel, "
384 (ins i32imm:$src0, R600_TReg32_Y:$src1, R600_TReg32_X:$src2),
385 "INTERP_PAIR_XY $src0 $src1 $src2 : $dst0 dst1",
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| H A D | VOP2Instructions.td | 15 bits<9> src0;
18 let Inst{8-0} = !if(P.HasSrc0, src0, 0);
27 bits<9> src0;
31 let Inst{8-0} = !if(P.HasSrc0, src0, 0);
123 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod),
124 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))),
126 [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]);
207 (inst ps.Pfl.DstRC:$vdst, ps.Pfl.Src0RC32:$src0,
248 (inst ps.Pfl.DstRC:$vdst, ps.Pfl.Src0RC32:$src0,
254 ps.Pfl.Src0RC32:$src0, ps.Pfl.Src1RC32:$src1, clampmod:$clamp)>,
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| H A D | VOP3Instructions.td | 14 dag src0 = !if(P.HasOMod,
15 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod),
16 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp));
19 (DivergentFragOrOp<node, P>.ret (P.Src0VT src0),
24 (DivergentFragOrOp<node, P>.ret (P.Src0VT src0),
28 (DivergentFragOrOp<node, P>.ret (P.Src0VT src0)))];
36 dag src0_dag = (P.Src0VT (VOP3PMods P.Src0VT:$src0, i32:$src0_modifiers));
63 (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers)),
68 (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers)),
72 (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers))))];
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| H A D | VOPInstructions.td | 183 bits<9> src0;
196 let Inst{40-32} = !if(P.HasSrc0, src0, 0);
250 // NB: For V_INTERP* opcodes, src0 is encoded as src1 and vice versa
256 let Inst{8} = 0; // No modifiers for src0
266 let Inst{49-41} = src0;
279 let Inst{49-41} = src0;
287 bits<9> src0;
298 let Inst{40-32} = !if(P.HasSrc0, src0, 0);
311 bits<9> src0;
319 let Inst{8} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0); // neg_hi src0
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| H A D | VOP3PInstructions.td | 23 (ins FP16InputMods:$src0_modifiers, VCSrc_f16:$src0,
98 (add (v2i16 (VOP3PMods v2i16:$src0, i32:$src0_modifiers)), NegSubInlineConstV216:$src1),
99 (V_PK_SUB_U16 $src0_modifiers, $src0, SRCMODS.OP_SEL_1, NegSubInlineConstV216:$src1)
104 (pat (v2i16 (VOP3PMods v2i16:$src0, i32:$src0_modifiers)),
106 (inst $src0_modifiers, $src0, $src1_modifiers, $src1, DSTCLAMP.ENABLE)
120 (f16 (fpround (fma_like (f32 (VOP3PMadMixMods f16:$src0, i32:$src0_modifiers)),
123 (mixlo_inst $src0_modifiers, $src0,
134 …(build_vector f16:$elt0, (fpround (fma_like (f32 (VOP3PMadMixMods f16:$src0, i32:$src0_modifiers)),
137 (v2f16 (mixhi_inst $src0_modifiers, $src0,
147 (AMDGPUclamp (fpround (fma_like (f32 (VOP3PMadMixMods f16:$src0, i32:$src0_modifiers)),
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| /netbsd-src/external/gpl3/binutils.old/dist/opcodes/ |
| H A D | bfin-dis.c | 559 decode_multfunc (int h0, int h1, int src0, int src1, disassemble_info *outf) in decode_multfunc() argument
564 s0 = dregs_hi (src0); in decode_multfunc()
566 s0 = dregs_lo (src0); in decode_multfunc()
580 decode_macfunc (int which, int op, int h0, int h1, int src0, int src1, disassemble_info *outf) in decode_macfunc() argument
606 decode_multfunc (h0, h1, src0, src1, outf); in decode_macfunc()
1653 int src0 = ((iw0 >> COMP3op_src0_bits) & COMP3op_src0_mask); in decode_COMP3op_0() local
1656 if (opc == 5 && src1 == src0) in decode_COMP3op_0()
1660 OUTS (outf, pregs (src0)); in decode_COMP3op_0()
1667 OUTS (outf, dregs (src0)); in decode_COMP3op_0()
1675 OUTS (outf, dregs (src0)); in decode_COMP3op_0()
[all …]
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| /netbsd-src/external/gpl3/binutils/dist/opcodes/ |
| H A D | bfin-dis.c | 559 decode_multfunc (int h0, int h1, int src0, int src1, disassemble_info *outf) in decode_multfunc() argument
564 s0 = dregs_hi (src0); in decode_multfunc()
566 s0 = dregs_lo (src0); in decode_multfunc()
580 decode_macfunc (int which, int op, int h0, int h1, int src0, int src1, disassemble_info *outf) in decode_macfunc() argument
606 decode_multfunc (h0, h1, src0, src1, outf); in decode_macfunc()
1653 int src0 = ((iw0 >> COMP3op_src0_bits) & COMP3op_src0_mask); in decode_COMP3op_0() local
1656 if (opc == 5 && src1 == src0) in decode_COMP3op_0()
1660 OUTS (outf, pregs (src0)); in decode_COMP3op_0()
1667 OUTS (outf, dregs (src0)); in decode_COMP3op_0()
1675 OUTS (outf, dregs (src0)); in decode_COMP3op_0()
[all …]
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| /netbsd-src/external/gpl3/gdb/dist/sim/testsuite/bfin/ |
| H A D | byteunpack.s | 8 .macro _bu_pre_test i0:req, src0:req, src1:req
10 imm32 R0, \src0
21 .macro bu_test i0:req, dst0:req, dst1:req, src0:req, src1:req
22 _bu_pre_test \i0, \src0, \src1
26 .macro bu_r_test i0:req, dst0:req, dst1:req, src0:req, src1:req
27 _bu_pre_test \i0, \src0, \src1
|
| /netbsd-src/sys/arch/luna68k/dev/ |
| H A D | omrasops.c | 819 * src0: source pointer in Plane0.
820 * if y-forward, src0 > dst0, point to left-top.
821 * if y-backward, src0 < dst0, point to left-bottom.
828 om4_rascopy_multi(uint8_t *dst0, uint8_t *src0, int16_t width, int16_t height) in om4_rascopy_multi() argument
884 " move.l (%[src0]),(%[dst0])+ ;\n" /* P0 */ in om4_rascopy_multi()
885 " adda.l %[PLANEOFFS],%[src0] ;\n" in om4_rascopy_multi()
886 " move.l (%[src0]),(%[dst1])+ ;\n" /* P1 */ in om4_rascopy_multi()
887 " adda.l %[PLANEOFFS],%[src0] ;\n" in om4_rascopy_multi()
888 " move.l (%[src0]),(%[dst2])+ ;\n" /* P2 */ in om4_rascopy_multi()
889 " adda.l %[PLANEOFFS],%[src0] ;\ in om4_rascopy_multi()
1206 uint8_t *src0 = src + OMFB_PLANEOFFS; om4_copyrows() local
[all...] |
| /netbsd-src/common/lib/libc/string/ |
| H A D | bcopy.c | 77 memcpy(void *dst0, const void *src0, size_t length) in memcpy() argument
80 memmove(void *dst0, const void *src0, size_t length) in memcpy()
83 bcopy(const void *src0, void *dst0, size_t length) in memcpy()
87 const char *src = src0; in memcpy()
133 _DIAGASSERT((unsigned long)src >= (unsigned long)src0); in memcpy()
|