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Searched refs:smu_set_hard_freq_range (Results 1 – 4 of 4) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/
H A Damdgpu_navi10_ppt.c1062 ret = smu_set_hard_freq_range(smu, SMU_UCLK, 0, max_freq); in navi10_pre_display_config_changed()
1489 ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0); in navi10_notify_smc_display_config()
1835 ret = smu_set_hard_freq_range(smu, SMU_UCLK, max_memory_clock, 0); in navi10_display_disable_memory_clock_switch()
1837 ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_memory_clock, 0); in navi10_display_disable_memory_clock_switch()
2267 ret = smu_set_hard_freq_range(smu, SMU_UCLK, 0, uclk_min); in navi10_disable_umc_cdr_12gbps_workaround()
2272 ret = smu_set_hard_freq_range(smu, SMU_UCLK, 0, uclk_max); in navi10_disable_umc_cdr_12gbps_workaround()
H A Damdgpu_smu_v11_0.c1357 ret = smu_set_hard_freq_range(smu, clk_select, clk_freq, 0); in smu_v11_0_display_clock_voltage_request()
H A Damdgpu_smu.c242 int smu_set_hard_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, in smu_set_hard_freq_range() function
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
H A Damdgpu_smu.h713 int smu_set_hard_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,