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Searched refs:set_reg_field_value (Results 1 – 23 of 23) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/
H A Damdgpu_dce110_opp_csc_v.c124 set_reg_field_value( in program_color_matrix_v()
135 set_reg_field_value( in program_color_matrix_v()
141 set_reg_field_value( in program_color_matrix_v()
153 set_reg_field_value( in program_color_matrix_v()
159 set_reg_field_value( in program_color_matrix_v()
171 set_reg_field_value( in program_color_matrix_v()
177 set_reg_field_value( in program_color_matrix_v()
189 set_reg_field_value( in program_color_matrix_v()
195 set_reg_field_value( in program_color_matrix_v()
207 set_reg_field_value( in program_color_matrix_v()
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H A Damdgpu_dce110_opp_regamma_v.c49 set_reg_field_value( in power_on_lut()
55 set_reg_field_value( in power_on_lut()
62 set_reg_field_value( in power_on_lut()
68 set_reg_field_value( in power_on_lut()
98 set_reg_field_value( in set_bypass_input_gamma()
112 set_reg_field_value( in configure_regamma_mode()
144 set_reg_field_value( in regamma_config_regions_and_segments()
150 set_reg_field_value( in regamma_config_regions_and_segments()
161 set_reg_field_value( in regamma_config_regions_and_segments()
172 set_reg_field_value( in regamma_config_regions_and_segments()
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H A Damdgpu_dce110_timing_generator.c119 set_reg_field_value(regval, early_cntl, in dce110_timing_generator_set_early_control()
139 set_reg_field_value( in dce110_timing_generator_enable_crtc()
164 set_reg_field_value( in dce110_timing_generator_program_blank_color()
169 set_reg_field_value( in dce110_timing_generator_program_blank_color()
174 set_reg_field_value( in dce110_timing_generator_program_blank_color()
270 set_reg_field_value(regval, 0, CRTC_COUNT_CONTROL, in program_horz_count_by_2()
274 set_reg_field_value(regval, 1, CRTC_COUNT_CONTROL, in program_horz_count_by_2()
396 set_reg_field_value(v_total_max, in dce110_timing_generator_set_drr()
401 set_reg_field_value(v_total_min, in dce110_timing_generator_set_drr()
406 set_reg_field_value(v_total_cntl, in dce110_timing_generator_set_drr()
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H A Damdgpu_dce110_mem_input_v.c54 set_reg_field_value(value, 1, in set_flip_control()
75 set_reg_field_value(value, temp, in program_pri_addr_c()
89 set_reg_field_value(value, temp, in program_pri_addr_c()
111 set_reg_field_value(value, temp, in program_pri_addr_l()
125 set_reg_field_value(value, temp, in program_pri_addr_l()
164 set_reg_field_value(value, 1, UNP_GRPH_ENABLE, GRPH_ENABLE); in enable()
177 set_reg_field_value(value, info->gfx8.num_banks, in program_tiling()
180 set_reg_field_value(value, info->gfx8.bank_width, in program_tiling()
183 set_reg_field_value(value, info->gfx8.bank_height, in program_tiling()
186 set_reg_field_value(value, info->gfx8.tile_aspect, in program_tiling()
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H A Damdgpu_dce110_transform_v.c96 set_reg_field_value( in program_viewport()
101 set_reg_field_value( in program_viewport()
110 set_reg_field_value( in program_viewport()
115 set_reg_field_value( in program_viewport()
126 set_reg_field_value( in program_viewport()
131 set_reg_field_value( in program_viewport()
140 set_reg_field_value( in program_viewport()
145 set_reg_field_value( in program_viewport()
172 set_reg_field_value(value, data->taps.h_taps - 1, in setup_scaling_configuration()
174 set_reg_field_value(value, data->taps.v_taps - 1, in setup_scaling_configuration()
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H A Damdgpu_dce110_timing_generator_v.c68 set_reg_field_value(value, 0, in dce110_timing_generator_v_enable_crtc()
78 set_reg_field_value(value, 1, in dce110_timing_generator_v_enable_crtc()
92 set_reg_field_value(value, 0, in dce110_timing_generator_v_disable_crtc()
94 set_reg_field_value(value, 0, in dce110_timing_generator_v_disable_crtc()
110 set_reg_field_value( in dce110_timing_generator_v_blank_crtc()
116 set_reg_field_value( in dce110_timing_generator_v_blank_crtc()
130 set_reg_field_value( in dce110_timing_generator_v_unblank_crtc()
136 set_reg_field_value( in dce110_timing_generator_v_unblank_crtc()
266 set_reg_field_value( in dce110_timing_generator_v_program_blanking()
275 set_reg_field_value( in dce110_timing_generator_v_program_blanking()
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H A Damdgpu_dce110_compressor.c95 set_reg_field_value(value, 3, LB_SYNC_RESET_SEL, LB_SYNC_RESET_SEL); in reset_lb_on_vblank()
96 set_reg_field_value(value, 1, LB_SYNC_RESET_SEL, LB_SYNC_RESET_SEL2); in reset_lb_on_vblank()
112 set_reg_field_value(value, 2, LB_SYNC_RESET_SEL, LB_SYNC_RESET_SEL); in reset_lb_on_vblank()
113 set_reg_field_value(value, 0, LB_SYNC_RESET_SEL, LB_SYNC_RESET_SEL2); in reset_lb_on_vblank()
154 set_reg_field_value(value, 0, FBC_CNTL, FBC_GRPH_COMP_EN); in dce110_compressor_power_up_fbc()
155 set_reg_field_value(value, 1, FBC_CNTL, FBC_EN); in dce110_compressor_power_up_fbc()
156 set_reg_field_value(value, 2, FBC_CNTL, FBC_COHERENCY_MODE); in dce110_compressor_power_up_fbc()
159 set_reg_field_value( in dce110_compressor_power_up_fbc()
169 set_reg_field_value(value, 1, FBC_COMP_MODE, FBC_RLE_EN); in dce110_compressor_power_up_fbc()
170 set_reg_field_value(value, 1, FBC_COMP_MODE, FBC_DPCM4_RGB_EN); in dce110_compressor_power_up_fbc()
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H A Damdgpu_dce110_hw_sequencer.c134 set_reg_field_value( in dce110_init_pte()
140 set_reg_field_value( in dce110_init_pte()
146 set_reg_field_value( in dce110_init_pte()
169 set_reg_field_value( in dce110_init_pte()
175 set_reg_field_value( in dce110_init_pte()
181 set_reg_field_value( in dce110_init_pte()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
H A Damdgpu_dce_audio.c307 set_reg_field_value(value, capable, in set_high_bit_rate_capable()
326 set_reg_field_value(value, latency_in_ms, in set_video_latency()
349 set_reg_field_value(value, latency_in_ms, in set_audio_latency()
362 set_reg_field_value(value, 1, in dce_aud_az_enable()
365 set_reg_field_value(value, 1, in dce_aud_az_enable()
370 set_reg_field_value(value, 0, in dce_aud_az_enable()
385 set_reg_field_value(value, 1, in dce_aud_az_disable()
390 set_reg_field_value(value, 0, in dce_aud_az_disable()
395 set_reg_field_value(value, 0, in dce_aud_az_disable()
422 set_reg_field_value(value, 1, in dce_aud_az_configure()
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H A Damdgpu_dce_link_encoder.c505 set_reg_field_value(value, hpd_source, AUX_CONTROL, AUX_HPD_SEL); in aux_initialize()
506 set_reg_field_value(value, 0, AUX_CONTROL, AUX_LS_READ_EN); in aux_initialize()
513 set_reg_field_value(value, 1, in aux_initialize()
1385 set_reg_field_value(value, 1, DC_HPD_CONTROL, DC_HPD_EN); in dce110_link_encoder_enable_hpd()
1395 set_reg_field_value(value, 0, DC_HPD_CONTROL, DC_HPD_EN); in dce110_link_encoder_disable_hpd()
H A Damdgpu_dce_aux.c124 set_reg_field_value( in acquire_engine()
132 set_reg_field_value( in acquire_engine()
147 set_reg_field_value( in acquire_engine()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce112/
H A Damdgpu_dce112_compressor.c127 set_reg_field_value( in lpt_memory_control_config()
134 set_reg_field_value( in lpt_memory_control_config()
158 set_reg_field_value( in lpt_memory_control_config()
165 set_reg_field_value( in lpt_memory_control_config()
172 set_reg_field_value( in lpt_memory_control_config()
179 set_reg_field_value( in lpt_memory_control_config()
205 set_reg_field_value( in lpt_memory_control_config()
212 set_reg_field_value( in lpt_memory_control_config()
241 set_reg_field_value( in lpt_memory_control_config()
248 set_reg_field_value( in lpt_memory_control_config()
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H A Damdgpu_dce112_hw_sequencer.c96 set_reg_field_value( in dce112_init_pte()
102 set_reg_field_value( in dce112_init_pte()
108 set_reg_field_value( in dce112_init_pte()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce80/
H A Damdgpu_dce80_timing_generator.c104 set_reg_field_value( in program_pix_dur()
138 set_reg_field_value( in dce80_timing_generator_enable_advanced_request()
144 set_reg_field_value( in dce80_timing_generator_enable_advanced_request()
152 set_reg_field_value( in dce80_timing_generator_enable_advanced_request()
157 set_reg_field_value( in dce80_timing_generator_enable_advanced_request()
163 set_reg_field_value( in dce80_timing_generator_enable_advanced_request()
168 set_reg_field_value( in dce80_timing_generator_enable_advanced_request()
175 set_reg_field_value( in dce80_timing_generator_enable_advanced_request()
181 set_reg_field_value( in dce80_timing_generator_enable_advanced_request()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/
H A Damdgpu_dce120_hw_sequencer.c132 set_reg_field_value(
138 set_reg_field_value(
144 set_reg_field_value(
H A Damdgpu_dce120_timing_generator.c423 set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_MODE_ENABLE); in dce120_timing_generator_disable_vga()
424 set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_TIMING_SELECT); in dce120_timing_generator_disable_vga()
425 set_reg_field_value( in dce120_timing_generator_disable_vga()
427 set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_OVERSCAN_COLOR_EN); in dce120_timing_generator_disable_vga()
683 set_reg_field_value( in dce120_timing_generator_enable_advanced_request()
695 set_reg_field_value( in dce120_timing_generator_enable_advanced_request()
984 set_reg_field_value( in dce120_timing_generator_set_test_pattern()
994 set_reg_field_value( in dce120_timing_generator_set_test_pattern()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dce80/
H A Damdgpu_irq_service_dce80.c63 set_reg_field_value( in hpd_ack()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dce120/
H A Damdgpu_irq_service_dce120.c63 set_reg_field_value( in hpd_ack()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dcn20/
H A Damdgpu_irq_service_dcn20.c144 set_reg_field_value( in hpd_ack()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dcn10/
H A Damdgpu_irq_service_dcn10.c144 set_reg_field_value( in hpd_ack()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dcn21/
H A Damdgpu_irq_service_dcn21.c145 set_reg_field_value( in hpd_ack()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dce110/
H A Damdgpu_irq_service_dce110.c62 set_reg_field_value(value, current_status ? 0 : 1, in hpd_ack()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/
H A Ddm_services.h132 #define set_reg_field_value(reg_value, value, reg_name, reg_field)\ macro