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Searched refs:set_min_deep_sleep_dcfclk (Results 1 – 4 of 4) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn10/
H A Damdgpu_rv1_clk_mgr.c206 pp_smu->set_min_deep_sleep_dcfclk) { in rv1_update_clocks()
209 …pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, (new_clocks->dcfclk_deep_sleep_khz + 999) / 100… in rv1_update_clocks()
226 pp_smu->set_min_deep_sleep_dcfclk) { in rv1_update_clocks()
229 …pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, (new_clocks->dcfclk_deep_sleep_khz + 999) / 100… in rv1_update_clocks()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/
H A Ddm_pp_smu.h126 void (*set_min_deep_sleep_dcfclk)(struct pp_smu *pp, int mhz); member
186 enum pp_smu_status (*set_min_deep_sleep_dcfclk)(struct pp_smu *pp, int Mhz); member
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn20/
H A Damdgpu_dcn20_clk_mgr.c211 if (pp_smu && pp_smu->set_min_deep_sleep_dcfclk) in dcn2_update_clocks()
212 …pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, clk_mgr_base->clks.dcfclk_deep_sleep_khz / 1000… in dcn2_update_clocks()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_pp_smu.c995 funcs->rv_funcs.set_min_deep_sleep_dcfclk = in dm_pp_get_funcs()
1008 funcs->nv_funcs.set_min_deep_sleep_dcfclk = in dm_pp_get_funcs()