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Searched refs:setOpcode (Results 1 – 25 of 74) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCDuplexInfo.cpp713 Result.setOpcode(Hexagon::SA1_inc); in deriveSubInst()
719 Result.setOpcode(Hexagon::SA1_dec); in deriveSubInst()
726 Result.setOpcode(Hexagon::SA1_addsp); in deriveSubInst()
732 Result.setOpcode(Hexagon::SA1_addi); in deriveSubInst()
738 Result.setOpcode(Hexagon::SA1_addrx); in deriveSubInst()
744 Result.setOpcode(Hexagon::SS2_allocframe); in deriveSubInst()
749 Result.setOpcode(Hexagon::SA1_zxtb); in deriveSubInst()
754 Result.setOpcode(Hexagon::SA1_and1); in deriveSubInst()
760 Result.setOpcode(Hexagon::SA1_cmpeqi); in deriveSubInst()
769 Result.setOpcode(Hexagon::SA1_combine1i); in deriveSubInst()
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H A DHexagonMCCompound.cpp214 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
227 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
241 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
254 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
267 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
285 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
303 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
314 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
325 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/XCore/Disassembler/
H A DXCoreDisassembler.cpp280 Inst.setOpcode(XCore::STW_2rus); in Decode2OpInstructionFail()
283 Inst.setOpcode(XCore::LDW_2rus); in Decode2OpInstructionFail()
286 Inst.setOpcode(XCore::ADD_3r); in Decode2OpInstructionFail()
289 Inst.setOpcode(XCore::SUB_3r); in Decode2OpInstructionFail()
292 Inst.setOpcode(XCore::SHL_3r); in Decode2OpInstructionFail()
295 Inst.setOpcode(XCore::SHR_3r); in Decode2OpInstructionFail()
298 Inst.setOpcode(XCore::EQ_3r); in Decode2OpInstructionFail()
301 Inst.setOpcode(XCore::AND_3r); in Decode2OpInstructionFail()
304 Inst.setOpcode(XCore::OR_3r); in Decode2OpInstructionFail()
307 Inst.setOpcode(XCore::LDW_3r); in Decode2OpInstructionFail()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonAsmPrinter.cpp249 T.setOpcode(Inst.getOpcode()); in ScaleVectorOffset()
278 Inst.setOpcode(Hexagon::A2_addi); in HexagonProcessInstruction()
292 Inst.setOpcode(Hexagon::A2_paddif); in HexagonProcessInstruction()
299 Inst.setOpcode(Hexagon::A2_paddit); in HexagonProcessInstruction()
306 Inst.setOpcode(Hexagon::A2_paddifnew); in HexagonProcessInstruction()
313 Inst.setOpcode(Hexagon::A2_padditnew); in HexagonProcessInstruction()
320 Inst.setOpcode(Hexagon::A2_andir); in HexagonProcessInstruction()
336 TmpInst.setOpcode(Hexagon::L2_loadrdgp); in HexagonProcessInstruction()
352 TmpInst.setOpcode(Hexagon::L2_loadrigp); in HexagonProcessInstruction()
365 MappedInst.setOpcode(Hexagon::C2_or); in HexagonProcessInstruction()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/AsmParser/
H A DHexagonAsmParser.cpp165 MCB.setOpcode(Hexagon::BUNDLE); in HexagonAsmParser()
539 NewInst.setOpcode(MCI.getOpcode()); in canonicalizeImmediates()
1237 TmpInst.setOpcode(opCode); in makeCombineInst()
1344 Inst.setOpcode(Hexagon::A2_addi); in processInstruction()
1378 Inst.setOpcode(Hexagon::C2_cmpgti); in processInstruction()
1392 TmpInst.setOpcode(Hexagon::C2_cmpeq); in processInstruction()
1402 Inst.setOpcode(Hexagon::C2_cmpgtui); in processInstruction()
1413 Inst.setOpcode(Hexagon::A2_combinew); in processInstruction()
1423 Inst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrpt) in processInstruction()
1434 Inst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrptnew) in processInstruction()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/AsmParser/
H A DPPCAsmParser.cpp754 TmpInst.setOpcode((Opcode == PPC::DCBTx || Opcode == PPC::DCBTT) ? in ProcessInstruction()
766 TmpInst.setOpcode(PPC::DCBT); in ProcessInstruction()
776 TmpInst.setOpcode(PPC::DCBTST); in ProcessInstruction()
799 TmpInst.setOpcode(PPC::DCBF); in ProcessInstruction()
808 TmpInst.setOpcode(PPC::LA); in ProcessInstruction()
817 TmpInst.setOpcode(PPC::ADDI); in ProcessInstruction()
826 TmpInst.setOpcode(PPC::ADDIS); in ProcessInstruction()
835 TmpInst.setOpcode(PPC::ADDIC); in ProcessInstruction()
844 TmpInst.setOpcode(PPC::ADDIC_rec); in ProcessInstruction()
856 TmpInst.setOpcode(Opcode == PPC::EXTLWI ? PPC::RLWINM : PPC::RLWINM_rec); in ProcessInstruction()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/Disassembler/
H A DMipsDisassembler.cpp681 MI.setOpcode(Mips::BOVC); in DecodeAddiGroupBranch()
684 MI.setOpcode(Mips::BEQC); in DecodeAddiGroupBranch()
687 MI.setOpcode(Mips::BEQZALC); in DecodeAddiGroupBranch()
709 MI.setOpcode(Mips::BOVC_MMR6); in DecodePOP35GroupBranchMMR6()
716 MI.setOpcode(Mips::BEQC_MMR6); in DecodePOP35GroupBranchMMR6()
723 MI.setOpcode(Mips::BEQZALC_MMR6); in DecodePOP35GroupBranchMMR6()
754 MI.setOpcode(Mips::BNVC); in DecodeDaddiGroupBranch()
757 MI.setOpcode(Mips::BNEC); in DecodeDaddiGroupBranch()
760 MI.setOpcode(Mips::BNEZALC); in DecodeDaddiGroupBranch()
782 MI.setOpcode(Mips::BNVC_MMR6); in DecodePOP37GroupBranchMMR6()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64AsmPrinter.cpp1074 MI.setOpcode(Opcode); in LowerFAULTING_OP()
1103 MOVI.setOpcode(AArch64::MOVID); in EmitFMov0()
1112 FMov.setOpcode(AArch64::FMOVWHr); in EmitFMov0()
1117 FMov.setOpcode(AArch64::FMOVWSr); in EmitFMov0()
1122 FMov.setOpcode(AArch64::FMOVXDr); in EmitFMov0()
1187 MovZ.setOpcode(AArch64::MOVZXi); in emitInstruction()
1194 MovK.setOpcode(AArch64::MOVKXi); in emitInstruction()
1208 TmpInst.setOpcode(AArch64::MOVIv16b_ns); in emitInstruction()
1247 TmpInst.setOpcode(AArch64::BR); in emitInstruction()
1256 TmpInst.setOpcode(AArch64::B); in emitInstruction()
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H A DAArch64MCInstLower.cpp303 OutMI.setOpcode(MI->getOpcode()); in Lower()
314 OutMI.setOpcode(AArch64::RET); in Lower()
319 OutMI.setOpcode(AArch64::RET); in Lower()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/
H A DVEAsmPrinter.cpp86 SICInst.setOpcode(VE::SIC); in emitSIC()
94 BSICInst.setOpcode(VE::BSICrii); in emitBSIC()
106 LEAInst.setOpcode(VE::LEAzii); in emitLEAzzi()
118 LEASLInst.setOpcode(VE::LEASLzii); in emitLEASLzzi()
130 LEAInst.setOpcode(VE::LEAzii); in emitLEAzii()
143 LEASLInst.setOpcode(VE::LEASLrri); in emitLEASLrri()
155 Inst.setOpcode(Opcode); in emitBinary()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp2249 Inst.setOpcode(ARM::RFEDA); in DecodeMemMultipleWritebackInstruction()
2252 Inst.setOpcode(ARM::RFEDA_UPD); in DecodeMemMultipleWritebackInstruction()
2255 Inst.setOpcode(ARM::RFEDB); in DecodeMemMultipleWritebackInstruction()
2258 Inst.setOpcode(ARM::RFEDB_UPD); in DecodeMemMultipleWritebackInstruction()
2261 Inst.setOpcode(ARM::RFEIA); in DecodeMemMultipleWritebackInstruction()
2264 Inst.setOpcode(ARM::RFEIA_UPD); in DecodeMemMultipleWritebackInstruction()
2267 Inst.setOpcode(ARM::RFEIB); in DecodeMemMultipleWritebackInstruction()
2270 Inst.setOpcode(ARM::RFEIB_UPD); in DecodeMemMultipleWritebackInstruction()
2273 Inst.setOpcode(ARM::SRSDA); in DecodeMemMultipleWritebackInstruction()
2276 Inst.setOpcode(ARM::SRSDA_UPD); in DecodeMemMultipleWritebackInstruction()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVMCInstLower.cpp139 OutMI.setOpcode(RVV->BaseInstr); in lowerRISCVVMachineInstrToMCInst()
212 OutMI.setOpcode(MI->getOpcode()); in lowerRISCVMachineInstrToMCInst()
235 OutMI.setOpcode(RISCV::CSRRS); in lowerRISCVMachineInstrToMCInst()
241 OutMI.setOpcode(RISCV::CSRRS); in lowerRISCVMachineInstrToMCInst()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/Disassembler/
H A DHexagonDisassembler.cpp173 MI.setOpcode(Hexagon::BUNDLE); in getInstruction()
205 MI.setOpcode(Hexagon::S6_allocframe_to_raw); in remapInstruction()
213 MI.setOpcode(L6_deallocframe_map_to_raw); in remapInstruction()
221 MI.setOpcode(L6_return_map_to_raw); in remapInstruction()
229 MI.setOpcode(L4_return_map_to_raw_t); in remapInstruction()
237 MI.setOpcode(L4_return_map_to_raw_f); in remapInstruction()
245 MI.setOpcode(L4_return_map_to_raw_tnew_pt); in remapInstruction()
253 MI.setOpcode(L4_return_map_to_raw_fnew_pt); in remapInstruction()
261 MI.setOpcode(L4_return_map_to_raw_tnew_pnt); in remapInstruction()
269 MI.setOpcode(L4_return_map_to_raw_fnew_pnt); in remapInstruction()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp303 ITInst.setOpcode(ARM::t2IT); in flushPendingInstructions()
5770 case ARM::tBcc: Inst.setOpcode(ARM::tB); break; in cvtThumbBranches()
5771 case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break; in cvtThumbBranches()
5780 Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc); in cvtThumbBranches()
5784 Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc); in cvtThumbBranches()
5795 Inst.setOpcode(ARM::t2B); in cvtThumbBranches()
5802 Inst.setOpcode(ARM::t2Bcc); in cvtThumbBranches()
8680 TmpInst.setOpcode(Opcode); in processInstruction()
8698 TmpInst.setOpcode(ARM::LDRSBTi); in processInstruction()
8700 TmpInst.setOpcode(ARM::LDRHTi); in processInstruction()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsTargetStreamer.cpp172 TmpInst.setOpcode(Opcode); in emitR()
181 TmpInst.setOpcode(Opcode); in emitRX()
201 TmpInst.setOpcode(Opcode); in emitII()
212 TmpInst.setOpcode(Opcode); in emitRRX()
230 TmpInst.setOpcode(Opcode); in emitRRRX()
250 TmpInst.setOpcode(Opcode); in emitRRIII()
1164 TmpInst.setOpcode(Mips::LUi); in emitDirectiveCpLoad()
1176 TmpInst.setOpcode(Mips::ADDiu); in emitDirectiveCpLoad()
1189 TmpInst.setOpcode(Mips::ADDu); in emitDirectiveCpLoad()
1292 Inst.setOpcode(Mips::OR); in emitDirectiveCpreturn()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86MCInstLower.cpp336 Inst.setOpcode(Opcode); in SimplifyShortImmForm()
364 Inst.setOpcode(NewOpcode); in SimplifyMOVSX()
415 Inst.setOpcode(Opcode); in SimplifyShortMoveForm()
493 OutMI.setOpcode(MI->getOpcode()); in Lower()
525 OutMI.setOpcode(NewOpc); in Lower()
566 OutMI.setOpcode(NewOpc); in Lower()
580 OutMI.setOpcode(NewOpc); in Lower()
682 OutMI.setOpcode(NewOpc); in Lower()
754 OutMI.setOpcode(NewOpc); in Lower()
774 OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget())); in Lower()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsAsmPrinter.cpp123 TmpInst0.setOpcode(Mips::JALR64); in emitPseudoIndirectBranch()
128 TmpInst0.setOpcode(Mips::JRC16_MMR6); in emitPseudoIndirectBranch()
130 TmpInst0.setOpcode(Mips::JALR); in emitPseudoIndirectBranch()
135 TmpInst0.setOpcode(Mips::JR_MM); in emitPseudoIndirectBranch()
138 TmpInst0.setOpcode(Mips::JR); in emitPseudoIndirectBranch()
860 I.setOpcode(Mips::JAL); in EmitJal()
869 I.setOpcode(Opcode); in EmitInstrReg()
888 I.setOpcode(Opcode); in EmitInstrRegReg()
898 I.setOpcode(Opcode); in EmitInstrRegRegReg()
H A DMipsMCInstLower.cpp216 OutMI.setOpcode(Mips::LUi); in lowerLongBranchLUi()
254 OutMI.setOpcode(Opcode); in lowerLongBranchADDiu()
319 OutMI.setOpcode(MI->getOpcode()); in Lower()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVAsmBackend.cpp154 Res.setOpcode(RISCV::BEQ); in relaxInstruction()
161 Res.setOpcode(RISCV::BNE); in relaxInstruction()
168 Res.setOpcode(RISCV::JAL); in relaxInstruction()
174 Res.setOpcode(RISCV::JAL); in relaxInstruction()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMInstrInfo.cpp38 NopInst.setOpcode(ARM::HINT); in getNop()
43 NopInst.setOpcode(ARM::MOVr); in getNop()
H A DARMAsmPrinter.cpp1446 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16); in emitInstruction()
1477 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel in emitInstruction()
1804 TmpInst.setOpcode(Opc); in emitInstruction()
1819 TmpInst.setOpcode(ARM::LDRi12); in emitInstruction()
1832 TmpInst.setOpcode(ARM::LDRrs); in emitInstruction()
2186 TmpInstDSB.setOpcode(ARM::DSB); in emitInstruction()
2190 TmpInstISB.setOpcode(ARM::ISB); in emitInstruction()
2198 TmpInstDSB.setOpcode(ARM::t2DSB); in emitInstruction()
2204 TmpInstISB.setOpcode(ARM::t2ISB); in emitInstruction()
2214 TmpInstSB.setOpcode(ARM::SB); in emitInstruction()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/M68k/
H A DM68kMCInstLower.cpp147 OutMI.setOpcode(Opcode); in Lower()
168 OutMI.setOpcode(Opcode); in Lower()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCAsmPrinter.cpp781 TmpInst.setOpcode(PPC::LWZ); in emitInstruction()
798 TmpInst.setOpcode(PPC::ADD4); in emitInstruction()
811 TmpInst.setOpcode(PPC::LWZ); in emitInstruction()
870 TmpInst.setOpcode(PPC::LA); in emitInstruction()
894 TmpInst.setOpcode(PPC::LD); in emitInstruction()
927 TmpInst.setOpcode(PPC::ADDIS); in emitInstruction()
959 TmpInst.setOpcode(PPC::LWZ); in emitInstruction()
990 TmpInst.setOpcode(PPC::ADDIS8); in emitInstruction()
1029 TmpInst.setOpcode(PPC::LD); in emitInstruction()
1062 TmpInst.setOpcode(PPC::ADDI8); in emitInstruction()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDGPUMCInstLower.cpp186 OutMI.setOpcode(TII->pseudoToMCOpcode(AMDGPU::S_SWAPPC_B64)); in lower()
205 OutMI.setOpcode(MCOpcode); in lower()
362 OutMI.setOpcode(MI->getOpcode()); in lower()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MC/
H A DMCInstBuilder.h27 Inst.setOpcode(Opcode); in MCInstBuilder()

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