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Searched refs:sclk_table (Results 1 – 15 of 15) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
H A Damdgpu_smu7_hwmgr.c642 &data->dpm_table.sclk_table, in smu7_reset_dpm_tables()
700 data->dpm_table.sclk_table.count = 0; in smu7_setup_dpm_tables_v0()
703 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count-1].value != in smu7_setup_dpm_tables_v0()
705 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value = in smu7_setup_dpm_tables_v0()
707 …data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = (i == 0) ? 1 : 0; in smu7_setup_dpm_tables_v0()
708 data->dpm_table.sclk_table.count++; in smu7_setup_dpm_tables_v0()
794 data->dpm_table.sclk_table.count = 0; in smu7_setup_dpm_tables_v1()
796 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count - 1].value != in smu7_setup_dpm_tables_v1()
799 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value = in smu7_setup_dpm_tables_v1()
802 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = in smu7_setup_dpm_tables_v1()
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H A Damdgpu_process_pptables_v1_0.c422 phm_ppt_v1_clock_voltage_dependency_table *sclk_table; in get_sclk_voltage_dependency_table() local
436 sclk_table = kzalloc(table_size, GFP_KERNEL); in get_sclk_voltage_dependency_table()
438 if (NULL == sclk_table) in get_sclk_voltage_dependency_table()
441 sclk_table->count = (uint32_t)tonga_table->ucNumEntries; in get_sclk_voltage_dependency_table()
449 entries, sclk_table, i); in get_sclk_voltage_dependency_table()
468 sclk_table = kzalloc(table_size, GFP_KERNEL); in get_sclk_voltage_dependency_table()
470 if (NULL == sclk_table) in get_sclk_voltage_dependency_table()
473 sclk_table->count = (uint32_t)polaris_table->ucNumEntries; in get_sclk_voltage_dependency_table()
481 entries, sclk_table, i); in get_sclk_voltage_dependency_table()
491 *pp_tonga_sclk_dep_table = sclk_table; in get_sclk_voltage_dependency_table()
H A Dsmu7_hwmgr.h106 struct smu7_single_dpm_table sclk_table; member
H A Damdgpu_vega10_hwmgr.c3329 struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); in vega10_find_dpm_states_clocks_in_dpm_table() local
3337 for (i = 0; i < sclk_table->count; i++) { in vega10_find_dpm_states_clocks_in_dpm_table()
3338 if (sclk == sclk_table->dpm_levels[i].value) in vega10_find_dpm_states_clocks_in_dpm_table()
3342 if (i >= sclk_table->count) { in vega10_find_dpm_states_clocks_in_dpm_table()
3343 if (sclk > sclk_table->dpm_levels[i-1].value) { in vega10_find_dpm_states_clocks_in_dpm_table()
3345 sclk_table->dpm_levels[i-1].value = sclk; in vega10_find_dpm_states_clocks_in_dpm_table()
4537 struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); in vega10_print_clock_levels() local
4558 count = sclk_table->count; in vega10_print_clock_levels()
4561 i, sclk_table->dpm_levels[i].value / 100, in vega10_print_clock_levels()
4825 struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); in vega10_get_sclk_od() local
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H A Damdgpu_smu8_hwmgr.c1523 struct phm_clock_voltage_dependency_table *sclk_table = in smu8_print_clock_levels() local
1535 for (i = 0; i < sclk_table->count; i++) in smu8_print_clock_levels()
1537 i, sclk_table->entries[i].clk / 100, in smu8_print_clock_levels()
H A Damdgpu_vega12_hwmgr.c2516 struct vega12_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
2519 int value = sclk_table->dpm_levels[sclk_table->count - 1].value;
H A Damdgpu_vega20_hwmgr.c1452 struct vega20_single_dpm_table *sclk_table = in vega20_get_sclk_od() local
1456 int value = sclk_table->dpm_levels[sclk_table->count - 1].value; in vega20_get_sclk_od()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
H A Damdgpu_vegam_smumgr.c890 for (i = 0; i < dpm_table->sclk_table.count; i++) { in vegam_populate_all_graphic_levels()
893 dpm_table->sclk_table.dpm_levels[i].value, in vegam_populate_all_graphic_levels()
911 (uint8_t)dpm_table->sclk_table.count; in vegam_populate_all_graphic_levels()
913 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in vegam_populate_all_graphic_levels()
915 for (i = 0; i < dpm_table->sclk_table.count; i++) in vegam_populate_all_graphic_levels()
924 for (i = 0; i < dpm_table->sclk_table.count; i++) in vegam_populate_all_graphic_levels()
949 for (i = 2; i < dpm_table->sclk_table.count; i++) in vegam_populate_all_graphic_levels()
1289 for (i = 0; i < hw_data->dpm_table.sclk_table.count; i++) { in vegam_program_memory_timing_parameters()
1292 hw_data->dpm_table.sclk_table.dpm_levels[i].value, in vegam_program_memory_timing_parameters()
1376 result = phm_find_boot_level(&(data->dpm_table.sclk_table), in vegam_populate_smc_boot_level()
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H A Damdgpu_polaris10_smumgr.c1006 for (i = 0; i < dpm_table->sclk_table.count; i++) { in polaris10_populate_all_graphic_levels()
1009 dpm_table->sclk_table.dpm_levels[i].value, in polaris10_populate_all_graphic_levels()
1024 (uint8_t)dpm_table->sclk_table.count; in polaris10_populate_all_graphic_levels()
1026 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in polaris10_populate_all_graphic_levels()
1034 for (i = 0; i < dpm_table->sclk_table.count; i++) in polaris10_populate_all_graphic_levels()
1059 for (i = 2; i < dpm_table->sclk_table.count; i++) in polaris10_populate_all_graphic_levels()
1375 for (i = 0; i < hw_data->dpm_table.sclk_table.count; i++) { in polaris10_program_memory_timing_parameters()
1378 hw_data->dpm_table.sclk_table.dpm_levels[i].value, in polaris10_program_memory_timing_parameters()
1464 result = phm_find_boot_level(&(data->dpm_table.sclk_table), in polaris10_populate_smc_boot_level()
1524 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = in polaris10_populate_clock_stretcher_data_table() local
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H A Damdgpu_tonga_smumgr.c715 for (i = 0; i < dpm_table->sclk_table.count; i++) { in tonga_populate_all_graphic_levels()
717 dpm_table->sclk_table.dpm_levels[i].value, in tonga_populate_all_graphic_levels()
731 if (dpm_table->sclk_table.count > 1) in tonga_populate_all_graphic_levels()
732 smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark = in tonga_populate_all_graphic_levels()
736 (uint8_t)dpm_table->sclk_table.count; in tonga_populate_all_graphic_levels()
738 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in tonga_populate_all_graphic_levels()
745 for (i = 0; i < dpm_table->sclk_table.count; i++) { in tonga_populate_all_graphic_levels()
775 for (i = 2; i < dpm_table->sclk_table.count; i++) in tonga_populate_all_graphic_levels()
1502 for (i = 0; i < data->dpm_table.sclk_table.count; i++) { in tonga_program_memory_timing_parameters()
1505 (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value, in tonga_program_memory_timing_parameters()
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H A Damdgpu_fiji_smumgr.c1029 for (i = 0; i < dpm_table->sclk_table.count; i++) { in fiji_populate_all_graphic_levels()
1031 dpm_table->sclk_table.dpm_levels[i].value, in fiji_populate_all_graphic_levels()
1045 levels[dpm_table->sclk_table.count - 1].DisplayWatermark = in fiji_populate_all_graphic_levels()
1049 (uint8_t)dpm_table->sclk_table.count; in fiji_populate_all_graphic_levels()
1051 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in fiji_populate_all_graphic_levels()
1058 for (i = 0; i < dpm_table->sclk_table.count; i++) in fiji_populate_all_graphic_levels()
1083 for (i = 2; i < dpm_table->sclk_table.count; i++) in fiji_populate_all_graphic_levels()
1323 data->dpm_table.sclk_table.dpm_levels[0].value; in fiji_populate_smc_acpi_level()
1539 for (i = 0; i < data->dpm_table.sclk_table.count; i++) { in fiji_program_memory_timing_parameters()
1542 data->dpm_table.sclk_table.dpm_levels[i].value, in fiji_program_memory_timing_parameters()
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H A Damdgpu_iceland_smumgr.c985 for (i = 0; i < dpm_table->sclk_table.count; i++) { in iceland_populate_all_graphic_levels()
987 dpm_table->sclk_table.dpm_levels[i].value, in iceland_populate_all_graphic_levels()
1001 if (dpm_table->sclk_table.count > 1) in iceland_populate_all_graphic_levels()
1002 smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark = in iceland_populate_all_graphic_levels()
1006 (uint8_t)dpm_table->sclk_table.count; in iceland_populate_all_graphic_levels()
1008 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in iceland_populate_all_graphic_levels()
1031 for (i = 2; i < dpm_table->sclk_table.count; i++) { in iceland_populate_all_graphic_levels()
1626 for (i = 0; i < data->dpm_table.sclk_table.count; i++) { in iceland_program_memory_timing_parameters()
1629 (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value, in iceland_program_memory_timing_parameters()
1662 result = phm_find_boot_level(&(data->dpm_table.sclk_table), in iceland_populate_smc_boot_level()
H A Damdgpu_ci_smumgr.c489 for (i = 0; i < dpm_table->sclk_table.count; i++) { in ci_populate_all_graphic_levels()
491 dpm_table->sclk_table.dpm_levels[i].value, in ci_populate_all_graphic_levels()
497 if (i == (dpm_table->sclk_table.count - 1)) in ci_populate_all_graphic_levels()
504 smu_data->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; in ci_populate_all_graphic_levels()
506 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in ci_populate_all_graphic_levels()
1663 for (i = 0; i < data->dpm_table.sclk_table.count; i++) { in ci_program_memory_timing_parameters()
1666 (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value, in ci_program_memory_timing_parameters()
1699 result = phm_find_boot_level(&(data->dpm_table.sclk_table), in ci_populate_smc_boot_level()
/netbsd-src/sys/external/bsd/drm2/dist/drm/radeon/
H A Dradeon_ci_dpm.c2561 for (i = 0; i < pi->dpm_table.sclk_table.count; i++) { in ci_do_program_memory_timing_parameters()
2564 pi->dpm_table.sclk_table.dpm_levels[i].value, in ci_do_program_memory_timing_parameters()
3295 for (i = 0; i < dpm_table->sclk_table.count; i++) { in ci_populate_all_graphic_levels()
3297 dpm_table->sclk_table.dpm_levels[i].value, in ci_populate_all_graphic_levels()
3304 if (i == (dpm_table->sclk_table.count - 1)) in ci_populate_all_graphic_levels()
3310 pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; in ci_populate_all_graphic_levels()
3312 ci_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in ci_populate_all_graphic_levels()
3470 &pi->dpm_table.sclk_table, in ci_setup_default_dpm_tables()
3485 pi->dpm_table.sclk_table.count = 0; in ci_setup_default_dpm_tables()
3488 (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value != in ci_setup_default_dpm_tables()
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H A Dci_dpm.h71 struct ci_single_dpm_table sclk_table; member