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Searched refs:sandybridge_pcode_write (Results 1 – 8 of 8) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/i915/gt/
H A Dintel_llc.c145 sandybridge_pcode_write(i915, in gen6_update_ring_freq()
H A Dintel_rc6.c263 ret = sandybridge_pcode_write(i915, GEN6_PCODE_WRITE_RC6VIDS, rc6vids); in gen6_rc6_enable()
/netbsd-src/sys/external/bsd/drm2/dist/drm/i915/
H A Dintel_sideband.h140 #define sandybridge_pcode_write(i915, mbox, val) \ macro
H A Dintel_pm.c3754 ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL, in intel_enable_sagv()
/netbsd-src/sys/external/bsd/drm2/dist/drm/i915/display/
H A Dintel_cdclk.c735 ret = sandybridge_pcode_write(dev_priv, in bdw_set_cdclk()
785 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, in bdw_set_cdclk()
1082 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, in skl_set_cdclk()
1580 ret = sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, in bxt_set_cdclk()
H A Dintel_hdcp.c224 ret = sandybridge_pcode_write(dev_priv, in intel_hdcp_load_keys()
H A Dintel_display_power.c4564 if (sandybridge_pcode_write(dev_priv, in hsw_write_dcomp()
H A Dintel_display.c6235 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, in hsw_enable_ips()
6264 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); in hsw_disable_ips()