/netbsd-src/external/gpl3/binutils/dist/include/opcode/ |
H A D | convex.h | 22 #define rrr 1 macro 93 {0,0,rrr,V,S,S}, /* mov */ 94 {0,0,rrr,S,S,V}, /* mov */ 95 {1,1,rrr,V,V,V}, /* merg.t */ 96 {2,1,rrr,V,V,V}, /* mask.t */ 97 {1,2,rrr,V,S,V}, /* merg.f */ 98 {2,2,rrr,V,S,V}, /* mask.f */ 99 {1,1,rrr,V,S,V}, /* merg.t */ 100 {2,1,rrr,V,S,V}, /* mask.t */ 101 {3,3,rrr,V,V,V}, /* mul.s */ [all …]
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/netbsd-src/external/gpl3/binutils.old/dist/include/opcode/ |
H A D | convex.h | 22 #define rrr 1 macro 93 {0,0,rrr,V,S,S}, /* mov */ 94 {0,0,rrr,S,S,V}, /* mov */ 95 {1,1,rrr,V,V,V}, /* merg.t */ 96 {2,1,rrr,V,V,V}, /* mask.t */ 97 {1,2,rrr,V,S,V}, /* merg.f */ 98 {2,2,rrr,V,S,V}, /* mask.f */ 99 {1,1,rrr,V,S,V}, /* merg.t */ 100 {2,1,rrr,V,S,V}, /* mask.t */ 101 {3,3,rrr,V,V,V}, /* mul.s */ [all …]
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
H A D | X86InstrXOP.td | 284 def rrr : IXOPi8Reg<opc, MRMSrcReg, (outs VR128:$dst), 319 []>, XOP_4V, VEX_W, Sched<[sched]>, FoldGenData<NAME#rrr>; 331 def rrr : IXOPi8Reg<opc, MRMSrcReg, (outs RC:$dst), 364 []>, XOP_4V, VEX_W, Sched<[sched]>, FoldGenData<NAME#rrr>;
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/netbsd-src/external/bsd/bzip2/dist/ |
H A D | decompress.c | 42 #define RETURN(rrr) \ argument 43 { retVal = rrr; goto save_state_and_return; };
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/netbsd-src/external/gpl3/gdb/dist/cpu/ |
H A D | epiphany.cpu | 2138 (define-pmacro (op-rrr name sem-op cond-op) 2200 (op-rrr add add add-vc) 2201 (op-rrr sub sub sub-vc) 2202 (op-rrr and and logic-vc) 2203 (op-rrr orr or logic-vc) 2204 (op-rrr eor xor logic-vc) 2280 (define-pmacro (shift-rrr name sem-op) 2319 (shift-rrr asr sra) 2320 (shift-rrr lsr srl) 2321 (shift-rrr lsl sll)
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/netbsd-src/external/gpl3/binutils/dist/cpu/ |
H A D | epiphany.cpu | 2138 (define-pmacro (op-rrr name sem-op cond-op) 2200 (op-rrr add add add-vc) 2201 (op-rrr sub sub sub-vc) 2202 (op-rrr and and logic-vc) 2203 (op-rrr orr or logic-vc) 2204 (op-rrr eor xor logic-vc) 2280 (define-pmacro (shift-rrr name sem-op) 2319 (shift-rrr asr sra) 2320 (shift-rrr lsr srl) 2321 (shift-rrr lsl sll)
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H A D | ChangeLog | 472 (op-rrr): Add NO-DIS attribute to .l. 473 (shift-rrr): Add NO-DIS attribute to .l.
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/netbsd-src/external/gpl3/gdb.old/dist/cpu/ |
H A D | epiphany.cpu | 2138 (define-pmacro (op-rrr name sem-op cond-op) 2200 (op-rrr add add add-vc) 2201 (op-rrr sub sub sub-vc) 2202 (op-rrr and and logic-vc) 2203 (op-rrr orr or logic-vc) 2204 (op-rrr eor xor logic-vc) 2280 (define-pmacro (shift-rrr name sem-op) 2319 (shift-rrr asr sra) 2320 (shift-rrr lsr srl) 2321 (shift-rrr lsl sll)
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/netbsd-src/external/gpl3/binutils.old/dist/cpu/ |
H A D | epiphany.cpu | 2138 (define-pmacro (op-rrr name sem-op cond-op) 2200 (op-rrr add add add-vc) 2201 (op-rrr sub sub sub-vc) 2202 (op-rrr and and logic-vc) 2203 (op-rrr orr or logic-vc) 2204 (op-rrr eor xor logic-vc) 2280 (define-pmacro (shift-rrr name sem-op) 2319 (shift-rrr asr sra) 2320 (shift-rrr lsr srl) 2321 (shift-rrr lsl sll)
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H A D | ChangeLog | 455 (op-rrr): Add NO-DIS attribute to .l. 456 (shift-rrr): Add NO-DIS attribute to .l.
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/netbsd-src/crypto/external/bsd/netpgp/dist/src/netpgpverify/ |
H A D | bzlib.c | 1128 #define RETURN(rrr) \ argument 1129 { retVal = rrr; goto save_state_and_return; };
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
H A D | AArch64SchedTSV110.td | 397 def : InstRW<[TSV110Wr_3cyc_1MDU, TSV110ReadMAW], (instregex "(S|U)(MADDL|MSUBL)rrr")>; 459 def : InstRW<[TSV110Wr_3cyc_1F], (instregex "^FCSEL(S|D)rrr$")>;
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H A D | AArch64SchedExynosM3.td | 540 M3ReadFMAC], (instregex "^FN?M(ADD|SUB)[DS]rrr")>; 543 def : InstRW<[M3WriteNEONH], (instregex "^FCSEL[DS]rrr")>;
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H A D | AArch64SchedExynosM5.td | 710 M5ReadFMACM1], (instregex "^FN?M(ADD|SUB)[HSD]rrr")>; 713 def : InstRW<[M5WriteNEONH], (instregex "^FCSEL[HSD]rrr")>;
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H A D | AArch64SchedExynosM4.td | 650 M4ReadFMACM1], (instregex "^FN?M(ADD|SUB)[SD]rrr")>; 654 def : InstRW<[M4WriteNEONH], (instregex "^FCSEL[HSD]rrr")>;
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H A D | AArch64SchedFalkorDetails.td | 1085 def : InstRW<[FalkorWr_1VX_1VY_4cyc], (instregex "^SHA1(C|M|P)rrr$")>; 1118 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^FCSEL(S|D)rrr$")>;
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H A D | AArch64SchedA57.td | 572 … InstRW<[A57WriteFPMA, A57ReadFPM, A57ReadFPM, A57ReadFPMA5], (instregex "^FN?M(ADD|SUB)[DS]rrr")>;
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H A D | AArch64SchedThunderX2T99.td | 530 (instregex "(S|U)(MADDL|MSUBL)rrr")>;
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H A D | AArch64SchedThunderX3T110.td | 790 (instregex "(S|U)(MADDL|MSUBL)rrr")>;
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H A D | AArch64SchedKryoDetails.td | 177 (instregex "(S|U)(MADDL|MSUBL)rrr")>;
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H A D | AArch64SchedA64FX.td | 918 (instregex "(S|U)(MADDL|MSUBL)rrr")>;
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
H A D | AVRInstrFormats.td | 292 // rrr = source register
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/ |
H A D | NVPTXInstrInfo.td | 998 def rrr : NVPTXInst<(outs RC:$dst), (ins RC:$a, RC:$b, RC:$c), 1020 def rrr : NVPTXInst<(outs RC:$dst), (ins RC:$a, RC:$b, RC:$c), 1358 def rrr
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
H A D | VEInstrInfo.td | 640 def rrr : RR<opc, (outs RC:$sx), (ins RC:$hi, RC:$sz, I32:$sy), 659 def rrr : RR<opc, (outs RC:$sx), (ins RC:$sz, RC:$low, I32:$sy),
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