Home
last modified time | relevance | path

Searched refs:res_pool (Results 1 – 25 of 37) sorted by relevance

12

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
H A Damdgpu_dcn20_hwseq.c71 if (dc->res_pool->gsl_groups.gsl_0 == 0) in find_free_gsl_group()
73 if (dc->res_pool->gsl_groups.gsl_1 == 0) in find_free_gsl_group()
75 if (dc->res_pool->gsl_groups.gsl_2 == 0) in find_free_gsl_group()
121 dc->res_pool->gsl_groups.gsl_0 = 1; in dcn20_setup_gsl_group_as_lock()
125 dc->res_pool->gsl_groups.gsl_1 = 1; in dcn20_setup_gsl_group_as_lock()
129 dc->res_pool->gsl_groups.gsl_2 = 1; in dcn20_setup_gsl_group_as_lock()
147 dc->res_pool->gsl_groups.gsl_0 = 0; in dcn20_setup_gsl_group_as_lock()
151 dc->res_pool->gsl_groups.gsl_1 = 0; in dcn20_setup_gsl_group_as_lock()
155 dc->res_pool->gsl_groups.gsl_2 = 0; in dcn20_setup_gsl_group_as_lock()
299 ASSERT(opp_id_src0 < dc->res_pool->res_cap->num_opp); in dcn20_init_blank()
[all …]
H A Damdgpu_dcn20_resource.c1587 const struct resource_pool *pool = dc->res_pool; in dcn20_add_dsc_to_stream_resource()
1590 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_add_dsc_to_stream_resource()
1625 release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc); in remove_dsc_from_stream_resource()
1837 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_populate_dml_writeback_from_context()
1892 for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) { in dcn20_populate_dml_pipes_from_context()
1908 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_populate_dml_pipes_from_context()
1924 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; in dcn20_populate_dml_pipes_from_context()
2198 dc->res_pool->funcs->populate_dml_writeback_from_context(dc, res_ctx, pipes); in dcn20_populate_dml_pipes_from_context()
2244 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_set_mcif_arb_params()
2290 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_validate_dsc()
[all …]
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
H A Damdgpu_dcn10_hw_sequencer.c81 const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; in print_microsec()
98 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn10_lock_all_pipes()
138 dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm); in dcn10_log_hubbub_state()
162 struct resource_pool *pool = dc->res_pool; in dcn10_log_hubp_states()
277 struct resource_pool *pool = dc->res_pool; in dcn10_log_hw_state()
662 struct hubp *hubp = dc->res_pool->hubps[0]; in undo_DEGVIDCN10_253_wa()
682 struct hubp *hubp = dc->res_pool->hubps[0]; in apply_DEGVIDCN10_253_wa()
691 for (i = 0; i < dc->res_pool->pipe_count; i++) { in apply_DEGVIDCN10_253_wa()
692 if (!dc->res_pool->hubps[i]->power_gated) in apply_DEGVIDCN10_253_wa()
719 if (dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled) in dcn10_bios_golden_init()
[all …]
H A Damdgpu_dcn10_hw_sequencer_debug.c85 const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; in dcn10_get_hubbub_state()
89 dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm); in dcn10_get_hubbub_state()
117 struct resource_pool *pool = dc->res_pool; in dcn10_get_hubp_states()
123 const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; in dcn10_get_hubp_states()
195 struct resource_pool *pool = dc->res_pool; in dcn10_get_rq_states()
237 struct resource_pool *pool = dc->res_pool; in dcn10_get_dlg_states()
294 struct resource_pool *pool = dc->res_pool; in dcn10_get_ttu_states()
334 struct resource_pool *pool = dc->res_pool; in dcn10_get_cm_states()
389 struct resource_pool *pool = dc->res_pool; in dcn10_get_mpcc_states()
420 struct resource_pool *pool = dc->res_pool; in dcn10_get_otg_states()
[all …]
H A Ddcn10_hw_sequencer.h149 struct resource_pool *res_pool,
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/
H A Damdgpu_dc.c722 dc->res_pool = dc_create_resource_pool(dc, init_params, dc_ctx->dce_version); in dc_construct()
723 if (!dc->res_pool) in dc_construct()
726 dc->clk_mgr = dc_clk_mgr_create(dc->ctx, dc->res_pool->pp_smu, dc->res_pool->dccg); in dc_construct()
730 if (dc->res_pool->funcs->update_bw_bounding_box) in dc_construct()
731 dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params); in dc_construct()
780 for (i = 0; i < dc->res_pool->pipe_count; i++) { in disable_dangling_plane()
856 full_pipe_count = dc->res_pool->pipe_count; in dc_create()
857 if (dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE) in dc_create()
861 dc->res_pool->stream_enc_count); in dc_create()
865 dc->caps.max_audios = dc->res_pool->audio_count; in dc_create()
[all …]
H A Damdgpu_dc_resource.c127 struct resource_pool *res_pool = NULL; in dc_create_resource_pool() local
131 res_pool = dce80_create_resource_pool( in dc_create_resource_pool()
135 res_pool = dce81_create_resource_pool( in dc_create_resource_pool()
139 res_pool = dce83_create_resource_pool( in dc_create_resource_pool()
143 res_pool = dce100_create_resource_pool( in dc_create_resource_pool()
147 res_pool = dce110_create_resource_pool( in dc_create_resource_pool()
153 res_pool = dce112_create_resource_pool( in dc_create_resource_pool()
158 res_pool = dce120_create_resource_pool( in dc_create_resource_pool()
165 res_pool = dcn10_create_resource_pool(init_data, dc); in dc_create_resource_pool()
170 res_pool = dcn20_create_resource_pool(init_data, dc); in dc_create_resource_pool()
[all …]
H A Damdgpu_dc_link.c441 struct audio_support *aud_support = &link->dc->res_pool->audio_support; in link_detect_sink()
759 struct audio_support *aud_support = &link->dc->res_pool->audio_support; in dc_link_detect_helper()
1280 if (link->dc->res_pool->funcs->link_init) in dc_link_construct()
1281 link->dc->res_pool->funcs->link_init(link); in dc_link_construct()
1358 link->link_enc = link->dc->res_pool->funcs->link_enc_create( in dc_link_construct()
2326 struct abm *abm = link->ctx->dc->res_pool->abm; in dc_link_get_backlight_level()
2339 struct abm *abm = dc->res_pool->abm; in dc_link_set_backlight_level()
2340 struct dmcu *dmcu = dc->res_pool->dmcu; in dc_link_set_backlight_level()
2392 struct abm *abm = dc->res_pool->abm; in dc_link_set_abm_disable()
2405 struct dmcu *dmcu = dc->res_pool->dmcu; in dc_link_set_psr_allow_active()
[all …]
H A Damdgpu_dc_debug.c319 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; in context_timing_trace()
323 for (i = 0; i < dc->res_pool->pipe_count; i++) { in context_timing_trace()
335 for (i = 0; i < dc->res_pool->pipe_count; i++) { in context_timing_trace()
H A Damdgpu_dc_surface.c160 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_plane_get_status()
172 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_plane_get_status()
H A Damdgpu_dc_link_hwss.c104 struct dmcu *dmcu = dc->res_pool->dmcu; in dp_enable_link_phy()
109 link->dc->res_pool->dp_clock_source; in dp_enable_link_phy()
216 struct dmcu *dmcu = dc->res_pool->dmcu; in dp_disable_link_phy()
H A Damdgpu_dc_stream.c396 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_add_writeback()
416 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_add_writeback()
427 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_add_writeback()
H A Damdgpu_dc_link_ddc.c664 if (ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout) in dc_link_aux_configure_timeout()
666 ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout(ddc, timeout); in dc_link_aux_configure_timeout()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/
H A Damdgpu_dce110_hw_sequencer.c208 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; in dce110_enable_display_power_gating()
1437 for (i = 0; i < dc->res_pool->stream_enc_count; i++) { in power_down_encoders()
1438 dc->res_pool->stream_enc[i]->funcs->dp_blank( in power_down_encoders()
1439 dc->res_pool->stream_enc[i]); in power_down_encoders()
1462 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { in power_down_controllers()
1463 dc->res_pool->timing_generators[i]->funcs->disable_crtc( in power_down_controllers()
1464 dc->res_pool->timing_generators[i]); in power_down_controllers()
1472 if (dc->res_pool->dp_clock_source->funcs->cs_power_down( in power_down_clock_sources()
1473 dc->res_pool->dp_clock_source) == false) in power_down_clock_sources()
1476 for (i = 0; i < dc->res_pool->clk_src_count; i++) { in power_down_clock_sources()
[all …]
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce100/
H A Damdgpu_dce100_hw_sequencer.c117 dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool); in dce100_prepare_bandwidth()
129 dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool); in dce100_optimize_bandwidth()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/
H A Damdgpu_dcn21_hwseq.c85 return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config); in dcn21_init_sys_ctx()
H A Damdgpu_dcn21_resource.c1060 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn21_calculate_wm()
1064 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; in dcn21_calculate_wm()
1089 if (dc->res_pool->funcs->populate_dml_pipes) in dcn21_calculate_wm()
1090 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, in dcn21_calculate_wm()
1139 …display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_par… in dcn21_validate_bandwidth()
1341 struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool); in update_bw_bounding_box()
1635 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn21_populate_dml_pipes_from_context()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn20/
H A Damdgpu_dcn20_clk_mgr.c114 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn20_update_clocks_update_dpp_dto()
164 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu; in dcn2_update_clocks()
180 if (dc->res_pool->pp_smu) in dcn2_update_clocks()
181 pp_smu = &dc->res_pool->pp_smu->nv_funcs; in dcn2_update_clocks()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce112/
H A Damdgpu_dce112_clk_mgr.c81 struct dmcu *dmcu = dc->res_pool->dmcu; in dce112_set_clock()
135 struct dmcu *dmcu = dc->res_pool->dmcu; in dce112_set_dispclk()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn10/
H A Damdgpu_rv1_clk_mgr_vbios_smu.c97 struct dmcu *dmcu = dc->res_pool->dmcu; in rv1_vbios_smu_set_dispclk()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn21/
H A Damdgpu_rn_clk_mgr_vbios_smu.c91 struct dmcu *dmcu = dc->res_pool->dmcu; in rn_vbios_smu_set_dispclk()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_mst_types.c554 params[i].sink->ctx->dc->res_pool->dscs[0], in set_dsc_configs_from_fairness_vars()
575 param.sink->ctx->dc->res_pool->dscs[0], in bpp_x16_from_pbn()
776 stream->sink->ctx->dc->res_pool->dscs[0], in compute_mst_dsc_configs_for_link()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
H A Ddce_clk_mgr.c259 struct dmcu *dmcu = clk_mgr_dce->base.ctx->dc->res_pool->dmcu; in dce_set_clock()
299 struct dmcu *dmcu = core_dc->res_pool->dmcu; in dce112_set_clock()
655 pp_display_cfg->disp_clk_khz = dc->res_pool->clk_mgr->clks.dispclk_khz; in dce11_pplib_apply_display_requirements()
H A Damdgpu_dce_aux.c446 struct dce_aux *aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]; in dce_aux_configure_timeout()
568 aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]; in dce_aux_transfer_raw()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce112/
H A Damdgpu_dce112_resource.c878 dc->res_pool->pipe_count, in dce112_validate_bandwidth()
950 dc->res_pool->dp_clock_source; in resource_map_phy_clock_resources()
953 &context->res_ctx, dc->res_pool, in resource_map_phy_clock_resources()
961 dc->res_pool, in resource_map_phy_clock_resources()

12