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Searched refs:ref_clock (Results 1 – 9 of 9) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
H A Damdgpu_vegam_smumgr.c727 uint32_t ref_clock; in vegam_calculate_sclk_params() local
751 ref_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev); in vegam_calculate_sclk_params()
763 ref_clock); in vegam_calculate_sclk_params()
766 do_div(temp, ref_clock); in vegam_calculate_sclk_params()
773 ref_clock); in vegam_calculate_sclk_params()
782 ref_clock); in vegam_calculate_sclk_params()
785 do_div(temp, ref_clock); in vegam_calculate_sclk_params()
H A Damdgpu_polaris10_smumgr.c852 uint32_t ref_clock; in polaris10_calculate_sclk_params() local
876 ref_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev); in polaris10_calculate_sclk_params()
886 …_int = (uint16_t)((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock); in polaris10_calculate_sclk_params()
889 do_div(temp, ref_clock); in polaris10_calculate_sclk_params()
894 …nt16_t)((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock); in polaris10_calculate_sclk_params()
901 …int16_t)((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock); in polaris10_calculate_sclk_params()
904 do_div(temp, ref_clock); in polaris10_calculate_sclk_params()
H A Damdgpu_fiji_smumgr.c872 uint32_t ref_clock; in fiji_calculate_sclk_params() local
885 ref_clock = atomctrl_get_reference_clock(hwmgr); in fiji_calculate_sclk_params()
918 uint32_t clk_s = ref_clock * 5 / in fiji_calculate_sclk_params()
H A Damdgpu_ci_smumgr.c310 uint32_t ref_clock; in ci_calculate_sclk_params() local
323 ref_clock = atomctrl_get_reference_clock(hwmgr); in ci_calculate_sclk_params()
350 uint32_t clk_s = ref_clock * 5 / in ci_calculate_sclk_params()
/netbsd-src/sys/external/bsd/drm2/dist/drm/i915/display/
H A Dintel_dpll_mgr.c2268 int ref_clock = dev_priv->cdclk.hw.ref; in cnl_hdmi_pll_ref_clock() local
2274 if (INTEL_GEN(dev_priv) >= 11 && ref_clock == 38400) in cnl_hdmi_pll_ref_clock()
2275 ref_clock = 19200; in cnl_hdmi_pll_ref_clock()
2277 return ref_clock; in cnl_hdmi_pll_ref_clock()
2286 u32 ref_clock; in cnl_ddi_calculate_wrpll() local
2319 ref_clock = cnl_hdmi_pll_ref_clock(dev_priv); in cnl_ddi_calculate_wrpll()
2321 cnl_wrpll_params_populate(wrpll_params, best_dco, ref_clock, in cnl_ddi_calculate_wrpll()
H A Dintel_ddi.c1380 u32 p0, p1, p2, dco_freq, ref_clock; in cnl_calc_wrpll_link() local
1419 ref_clock = cnl_hdmi_pll_ref_clock(dev_priv); in cnl_calc_wrpll_link()
1422 * ref_clock; in cnl_calc_wrpll_link()
1425 DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000; in cnl_calc_wrpll_link()
1458 u32 m1, m2_int, m2_frac, div1, div2, ref_clock; in icl_calc_mg_pll_link() local
1461 ref_clock = dev_priv->cdclk.hw.ref; in icl_calc_mg_pll_link()
1519 tmp = (u64)m1 * m2_int * ref_clock + in icl_calc_mg_pll_link()
1520 (((u64)m1 * m2_frac * ref_clock) >> 22); in icl_calc_mg_pll_link()
/netbsd-src/sys/external/bsd/drm2/dist/drm/radeon/
H A Dradeon_rv6xx_dpm.c530 static inline u32 rv6xx_calculate_vco_frequency(u32 ref_clock, in rv6xx_calculate_vco_frequency() argument
534 return ref_clock * ((dividers->fb_div & ~1) << fb_divider_scale) / in rv6xx_calculate_vco_frequency()
H A Dradeon_ci_dpm.c1996 u32 ref_clock = rdev->clock.spll.reference_freq; in ci_program_display_gap() local
2014 tmp = pre_vbi_time_in_us * (ref_clock / 100); in ci_program_display_gap()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
H A Damdgpu_smu7_hwmgr.c4082 uint32_t ref_clock, refresh_rate; in smu7_program_display_gap() local
4087 ref_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev); in smu7_program_display_gap()
4104 display_gap2 = pre_vbi_time_in_us * (ref_clock / 100); in smu7_program_display_gap()