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/netbsd-src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
H A Dstm32h743.dtsi45 #include <dt-bindings/mfd/stm32h7-rcc.h>
77 clocks = <&rcc TIM5_CK>;
85 clocks = <&rcc LPTIM1_CK>;
113 resets = <&rcc STM32H7_APB1L_RESET(SPI2)>;
114 clocks = <&rcc SPI2_CK>;
125 resets = <&rcc STM32H7_APB1L_RESET(SPI3)>;
126 clocks = <&rcc SPI3_CK>;
135 clocks = <&rcc USART2_CK>;
143 clocks = <&rcc USART3_CK>;
151 clocks = <&rcc UART4_CK>;
[all …]
H A Dstm32mp151.dtsi130 clocks = <&rcc TIM2_K>;
163 clocks = <&rcc TIM3_K>;
197 clocks = <&rcc TIM4_K>;
229 clocks = <&rcc TIM5_K>;
263 clocks = <&rcc TIM6_K>;
281 clocks = <&rcc TIM7_K>;
299 clocks = <&rcc TIM12_K>;
321 clocks = <&rcc TIM13_K>;
343 clocks = <&rcc TIM14_K>;
366 clocks = <&rcc LPTIM1_K>;
[all …]
H A Dstm32f429.dtsi50 #include <dt-bindings/mfd/stm32f4-rcc.h>
100 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
109 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
130 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
139 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
160 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
169 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
190 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
198 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
219 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
[all …]
H A Dstm32f746.dtsi45 #include <dt-bindings/mfd/stm32f7-rcc.h>
82 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
91 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
112 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
121 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
142 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
151 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
172 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
180 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
201 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
[all …]
H A Dstm32mp157.dtsi15 clocks = <&rcc GPU>, <&rcc GPU_K>;
17 resets = <&rcc GPU_R>;
23 clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
25 resets = <&rcc DSI_R>;
H A Dstm32f7-pinctrl.dtsi8 #include <dt-bindings/mfd/stm32f7-rcc.h>
26 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
36 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
46 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
56 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
66 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
76 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
86 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
96 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
106 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
[all …]
H A Dstm32mp153.dtsi33 clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
46 clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
H A Dstm32f4-pinctrl.dtsi44 #include <dt-bindings/mfd/stm32f4-rcc.h>
62 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
72 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
82 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
92 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>;
102 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOE)>;
112 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOF)>;
122 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOG)>;
132 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOH)>;
142 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOI)>;
[all …]
H A Dstm32f769-disco.dts91 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>;
103 &rcc {
104 compatible = "st,stm32f769-rcc", "st,stm32f746-rcc", "st,stm32-rcc";
H A Dstm32mp157c-odyssey.dts33 assigned-clocks = <&rcc ETHCK_K>, <&rcc PLL4_P>;
34 assigned-clock-parents = <&rcc PLL4_P>;
H A Dstm32mp15xc.dtsi13 clocks = <&rcc CRYP1>;
14 resets = <&rcc CRYP1_R>;
H A Dstm32f469.dtsi11 resets = <&rcc STM32F4_APB2_RESET(DSI)>;
13 clocks = <&rcc 1 CLK_F469_DSI>, <&clk_hse>;
H A Dstm32mp15xx-dkx.dtsi431 clocks = <&rcc SPI2>, <&rcc SPI2_K>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
494 clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
504 clocks = <&rcc SAI2_K>;
522 clocks = <&rcc SAI2_K>, <&sai2a>;
H A Dstm32mp15xx-dhcom-pdk2.dtsi228 clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
238 clocks = <&rcc SAI2_K>;
256 clocks = <&rcc SAI2_K>, <&sai2a>;
H A Dstm32f469-disco.dts127 &rcc {
128 compatible = "st,stm32f469-rcc", "st,stm32f42xx-rcc", "st,stm32-rcc";
H A Dstm32mp15xx-dhcor-avenger96.dtsi289 clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
299 clocks = <&rcc SAI2_K>;
H A Dstm32f429-disco.dts169 assigned-clocks = <&rcc 1 CLK_RTC>;
170 assigned-clock-parents = <&rcc 1 CLK_LSI>;
H A Dstm32f746-disco.dts70 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>;
H A Dstm32h743i-eval.dts84 clocks = <&rcc USB1ULPI_CK>;
H A Dstm32746g-eval.dts133 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>;
/netbsd-src/sys/stand/
H A Dcopy.c54 register int from, to, record, rcc, wcc, bsize = BSIZE; in main() local
60 if (!(rcc = read(from, buf, bsize))) in main()
62 if (rcc < 0) { in main()
67 if (rcc != bsize) { in main()
69 bsize = rcc; in main()
74 record, bsize, rcc); in main()
78 if (rcc > bsize) in main()
79 rcc = bsize; in main()
81 if ((wcc = write(to, buf, rcc)) < 0) { in main()
86 if (wcc < rcc) { in main()
[all …]
/netbsd-src/lib/libc/citrus/
H A Dcitrus_ctype.c142 _citrus_ctype_open(_citrus_ctype_t *rcc, in _citrus_ctype_open() argument
152 _DIAGASSERT(rcc != NULL); in _citrus_ctype_open()
155 *rcc = &_citrus_ctype_default; in _citrus_ctype_open()
175 *rcc = cc; in _citrus_ctype_open()
199 _citrus_ctype_open(_citrus_ctype_t *rcc, in _citrus_ctype_open() argument
204 *rcc = &_citrus_ctype_default; in _citrus_ctype_open()
/netbsd-src/sys/kern/
H A Dkern_cctr.c187 int64_t rcc; in cc_get_timecount() local
193 rcc = cpu_counter32() - curcpu()->ci_cc.cc_delta; in cc_get_timecount()
196 return rcc; in cc_get_timecount()
/netbsd-src/external/bsd/file/dist/magic/magdir/
H A Dqt11 # src/tools/rcc/rcc.cpp#L840
/netbsd-src/distrib/common/
H A Dprotocols13 bbn-rcc-mon 10 BBN-RCC-MON

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