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Searched refs:radeon_get_ib_value (Results 1 – 9 of 9) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/radeon/
H A Dradeon_r600_cs.c854 wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1); in r600_cs_common_vline_parse()
870 if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != vline_status[0]) { in r600_cs_common_vline_parse()
875 if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != RADEON_VLINE_STAT) { in r600_cs_common_vline_parse()
889 header = radeon_get_ib_value(p, h_idx); in r600_cs_common_vline_parse()
890 crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1); in r600_cs_common_vline_parse()
1029 track->sq_config = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1032 track->db_depth_control = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1044 track->db_depth_info = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1055 track->db_depth_info = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1060 track->db_depth_view = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
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H A Dradeon_evergreen_cs.c793 texdw[0] = radeon_get_ib_value(p, idx + 0); in evergreen_cs_track_validate_texture()
794 texdw[1] = radeon_get_ib_value(p, idx + 1); in evergreen_cs_track_validate_texture()
795 texdw[2] = radeon_get_ib_value(p, idx + 2); in evergreen_cs_track_validate_texture()
796 texdw[3] = radeon_get_ib_value(p, idx + 3); in evergreen_cs_track_validate_texture()
797 texdw[4] = radeon_get_ib_value(p, idx + 4); in evergreen_cs_track_validate_texture()
798 texdw[5] = radeon_get_ib_value(p, idx + 5); in evergreen_cs_track_validate_texture()
799 texdw[6] = radeon_get_ib_value(p, idx + 6); in evergreen_cs_track_validate_texture()
800 texdw[7] = radeon_get_ib_value(p, idx + 7); in evergreen_cs_track_validate_texture()
1181 track->db_depth_control = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1199 track->db_z_info = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
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H A Dradeon_vce.c536 offset = radeon_get_ib_value(p, lo); in radeon_vce_cs_reloc()
537 idx = radeon_get_ib_value(p, hi); in radeon_vce_cs_reloc()
623 uint32_t len = radeon_get_ib_value(p, p->idx); in radeon_vce_cs_parse()
624 uint32_t cmd = radeon_get_ib_value(p, p->idx + 1); in radeon_vce_cs_parse()
640 handle = radeon_get_ib_value(p, p->idx + 2); in radeon_vce_cs_parse()
659 *size = radeon_get_ib_value(p, p->idx + 8) * in radeon_vce_cs_parse()
660 radeon_get_ib_value(p, p->idx + 10) * in radeon_vce_cs_parse()
696 tmp = radeon_get_ib_value(p, p->idx + 4); in radeon_vce_cs_parse()
H A Dradeon_r300.c674 idx_value = radeon_get_ib_value(p, idx); in r300_packet0_check()
1230 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); in r300_packet3_check()
1241 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { in r300_packet3_check()
1245 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); in r300_packet3_check()
1256 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { in r300_packet3_check()
1260 track->vap_vf_cntl = radeon_get_ib_value(p, idx); in r300_packet3_check()
1268 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); in r300_packet3_check()
1275 track->vap_vf_cntl = radeon_get_ib_value(p, idx); in r300_packet3_check()
1282 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); in r300_packet3_check()
1289 track->vap_vf_cntl = radeon_get_ib_value(p, idx); in r300_packet3_check()
H A Dradeon_r100.c1297 value = radeon_get_ib_value(p, idx); in r100_reloc_pitch_offset()
1333 c = radeon_get_ib_value(p, idx++) & 0x1F; in r100_packet3_load_vbpntr()
1349 idx_value = radeon_get_ib_value(p, idx); in r100_packet3_load_vbpntr()
1350 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); in r100_packet3_load_vbpntr()
1362 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->gpu_offset); in r100_packet3_load_vbpntr()
1375 idx_value = radeon_get_ib_value(p, idx); in r100_packet3_load_vbpntr()
1376 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); in r100_packet3_load_vbpntr()
1467 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) { in r100_cs_packet_parse_vline()
1481 header = radeon_get_ib_value(p, h_idx); in r100_cs_packet_parse_vline()
1482 crtc_id = radeon_get_ib_value(p, h_idx + 5); in r100_cs_packet_parse_vline()
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H A Dradeon_cs.c761 header = radeon_get_ib_value(p, idx); in radeon_cs_packet_parse()
797 printk("\t0x%08x <---\n", radeon_get_ib_value(p, i)); in radeon_cs_packet_parse()
799 printk("\t0x%08x\n", radeon_get_ib_value(p, i)); in radeon_cs_packet_parse()
882 idx = radeon_get_ib_value(p, p3reloc.idx + 1); in radeon_cs_packet_next_reloc()
H A Dradeon_uvd.c590 offset = radeon_get_ib_value(p, data0); in radeon_uvd_cs_reloc()
591 idx = radeon_get_ib_value(p, data1); in radeon_uvd_cs_reloc()
606 cmd = radeon_get_ib_value(p, p->idx) >> 1; in radeon_uvd_cs_reloc()
H A Dradeon_r200.c166 idx_value = radeon_get_ib_value(p, idx); in r200_packet0_check()
H A Dradeon.h1136 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) in radeon_get_ib_value() function