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Searched refs:psr (Results 1 – 25 of 150) sorted by relevance

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/netbsd-src/sys/external/bsd/drm2/dist/drm/i915/display/
H A Dintel_psr.c90 switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) { in intel_psr2_enabled()
112 imr_reg = TRANS_PSR_IMR(dev_priv->psr.transcoder); in psr_irq_control()
114 trans_shift = dev_priv->psr.transcoder; in psr_irq_control()
119 if (dev_priv->psr.debug & I915_PSR_DEBUG_IRQ) in psr_irq_control()
169 enum transcoder cpu_transcoder = dev_priv->psr.transcoder; in intel_psr_irq_handler()
176 imr_reg = TRANS_PSR_IMR(dev_priv->psr.transcoder); in intel_psr_irq_handler()
178 trans_shift = dev_priv->psr.transcoder; in intel_psr_irq_handler()
183 dev_priv->psr.last_entry_attempt = time_ns; in intel_psr_irq_handler()
189 dev_priv->psr.last_exit = time_ns; in intel_psr_irq_handler()
195 bool psr2_enabled = dev_priv->psr.psr2_enabled; in intel_psr_irq_handler()
[all …]
H A Dintel_bios.c683 dev_priv->vbt.psr.enable = driver->psr_enabled; in parse_driver_features()
701 dev_priv->vbt.psr.enable = power->psr & BIT(panel_type); in parse_power_conservation_features()
827 const struct bdb_psr *psr; in parse_psr() local
831 psr = find_section(bdb, BDB_PSR); in parse_psr()
832 if (!psr) { in parse_psr()
837 psr_table = &psr->psr_table[panel_type]; in parse_psr()
839 dev_priv->vbt.psr.full_link = psr_table->full_link; in parse_psr()
840 dev_priv->vbt.psr.require_aux_wakeup = psr_table->require_aux_to_wakeup; in parse_psr()
843 dev_priv->vbt.psr.idle_frames = psr_table->idle_frames < 0 ? 0 : in parse_psr()
848 dev_priv->vbt.psr.lines_to_wait = PSR_0_LINES_TO_WAIT; in parse_psr()
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/netbsd-src/external/gpl3/gdb/dist/sim/testsuite/frv/
H A Dbreak.cgs24 test_spr_bits 0x4,2,0x1,psr ; psr.s is set
25 test_spr_bits 0x1,0,0x0,psr ; psr.et is clear
29 or_spr_immed 0x00000001,psr ; turn on psr.et
30 and_spr_immed 0xfffffffb,psr ; turn off psr.s
31 test_spr_bits 0x4,2,0x0,psr ; psr.s is clear
32 test_spr_bits 0x1,0,0x1,psr ; psr.et is set
36 test_spr_bits 0x4,2,0x0,psr ; psr.s is clear
37 test_spr_bits 0x1,0,0x1,psr ; psr.et is set
44 test_spr_bits 0x4,2,0x1,psr ; psr.s is set
45 test_spr_bits 0x1,0,0x0,psr ; psr.et is clear
[all …]
/netbsd-src/sys/arch/sparc/include/
H A Dpsl.h248 int psr; in getpsr() local
250 __asm volatile("rd %%psr,%0" : "=r" (psr)); in getpsr()
251 return (psr); in getpsr()
273 int psr, oldipl; in spl0() local
280 __asm volatile("rd %%psr,%0" : "=r" (psr) : : "memory"); in spl0()
281 oldipl = psr & PSR_PIL; in spl0()
282 __asm volatile("wr %0,%1,%%psr" : : "r" (psr), "r" (oldipl)); in spl0()
299 int psr; \
300 __asm volatile("rd %%psr,%0" : "=r" (psr)); \
301 psr &= ~PSR_PIL; \
[all …]
/netbsd-src/sys/arch/ia64/stand/efi/libefi/
H A Dexec.c99 u_int64_t psr; in disable_ic() local
100 __asm __volatile("mov %0=psr;;" : "=r" (psr)); in disable_ic()
102 return psr; in disable_ic()
106 restore_ic(u_int64_t psr) in restore_ic() argument
108 __asm __volatile("mov psr.l=%0;; srlz.i" :: "r" (psr)); in restore_ic()
117 u_int64_t psr; in enter_kernel() local
138 u_int64_t psr; in elf64_exec() local
179 psr = disable_ic(); in elf64_exec()
209 restore_ic(psr); in elf64_exec()
/netbsd-src/external/gpl3/gdb/dist/sim/testsuite/frv/interrupts/
H A Dreset.cgs11 and_spr_immed 0xfffffffb,psr ; turn off PSR.S
38 test_spr_bits 0x4,2,1,psr ; psr.s is set
39 test_spr_bits 0x2,1,0,psr ; psr.ps not set
72 test_spr_bits 0x4,2,1,psr ; psr.s is set
73 test_spr_bits 0x2,1,1,psr ; psr.ps is set
H A Dshadow_regs.cgs10 test_spr_bits 0x800,11,1,psr ; PSR.ESR set
11 test_spr_bits 0x4,2,1,psr ; PSR.S set
30 and_spr_immed 0xfffff7ff,psr ; turn off PSR.ESR
66 or_spr_immed 0x00000800,psr ; turn on PSR.ESR
85 and_spr_immed 0xfffffffb,psr ; turn off PSR.S
99 test_spr_bits 0x800,11,0,psr ; PSR.ESR clear
100 test_spr_bits 0x4,2,0,psr ; PSR.S clear
143 test_spr_bits 0x800,11,1,psr ; PSR.ESR set
144 test_spr_bits 0x4,2,1,psr ; PSR.S set
154 and_spr_immed 0xfffff7ff,psr ; turn off PSR.ESR
[all …]
/netbsd-src/sys/arch/ia64/ia64/
H A Dtrap.c227 printpsr(uint64_t psr) in printpsr() argument
229 printbits(psr, psr_bits, sizeof(psr_bits)/sizeof(psr_bits[0])); in printpsr()
264 printf(" cr.ipsr = 0x%lx (", tf->tf_special.psr); in printtrap()
265 printpsr(tf->tf_special.psr); in printtrap()
271 if (tf->tf_special.psr & IA64_PSR_IS) { in printtrap()
301 slot = ((tf->tf_special.psr & IA64_PSR_RI) == IA64_PSR_RI_0) ? 0 : in trap_decode_break()
302 ((tf->tf_special.psr & IA64_PSR_RI) == IA64_PSR_RI_1) ? 1 : 2; in trap_decode_break()
520 tf->tf_special.psr &= ~IA64_PSR_SS; in trap()
592 tf->tf_special.psr &= ~IA64_PSR_RI; in trap()
615 tf->tf_special.psr &= ~IA64_PSR_RI; in trap()
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H A Dpal.S59 mov psrsave=psr
71 rsm psr.i // disable interrupts
74 2: mov psr.l=psrsave
155 mov psrsave=psr
166 rsm psr.i // disable interrupts
169 mov psr.l=psrsave
H A Dmachdep.c268 uint64_t psr; in map_vhpt() local
283 __asm __volatile("mov %0=psr" : "=r"(psr)); in map_vhpt()
290 __asm __volatile("mov psr.l=%0" :: "r" (psr)); in map_vhpt()
298 uint64_t psr; in map_pal_code() local
311 __asm __volatile("mov %0=psr" : "=r"(psr)); in map_pal_code()
322 __asm __volatile("mov psr.l=%0" :: "r" (psr)); in map_pal_code()
330 uint64_t psr; in map_gateway_page() local
339 __asm __volatile("mov %0=psr" : "=r"(psr)); in map_gateway_page()
348 __asm __volatile("mov psr.l=%0" :: "r" (psr)); in map_gateway_page()
787 tf->tf_special.psr = IA64_PSR_IC | IA64_PSR_I | IA64_PSR_IT | in setregs()
H A Dexception.S305 rsm psr.dt
547 ssm psr.dt|psr.ic|psr.dfh
567 rsm psr.i
576 rsm psr.dt|psr.ic
754 ssm psr.dt
817 (p11) ssm psr.i ; \
890 1: rsm psr.dt // turn off data translations
934 ssm psr.dt
945 9: ssm psr.dt
976 1: rsm psr.dt // turn off data translations
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H A Ddb_interface.c165 slot = (f->tf_special.psr >> 41) & 3; in db_getip()
175 f->tf_special.psr &= ~IA64_PSR_RI; in db_getip()
176 f->tf_special.psr |= slot << 41; in db_getip()
233 {"psr", DB_OFFSET(tf_special.psr), db_frame},
428 regs->tf_special.psr += IA64_PSR_RI_1; in db_pc_advance()
429 if ((regs->tf_special.psr & IA64_PSR_RI) > IA64_PSR_RI_2) { in db_pc_advance()
430 regs->tf_special.psr &= ~IA64_PSR_RI; in db_pc_advance()
/netbsd-src/sys/external/bsd/gnu-efi/dist/lib/ia64/
H A Dpalproc.S55 mov r2 = psr;;
77 mov psr.l = r2
94 mov psr.l = loc5;;
135 mov r2 = psr;;
138 mov psr.l = r2
153 mov psr.l = loc5;;
/netbsd-src/sys/arch/sparc/sparc/
H A Dlock_stubs.s130 rd %psr, %o1
137 wr %o2, %o1, %psr
177 rd %psr, %o1
179 wr %o3, %o1, %psr
200 rd %psr, %o4 ! disable interrupts
202 wr %o5, 0, %psr
225 wr %o4, 0, %psr ! enable interrupts
233 wr %o4, 0, %psr ! enable interrupts
H A Dlocore.s297 mov (type), %l3; b label; mov %psr, %l0; nop
301 mov (lev), %l3; b _C_LABEL(sparc_interrupt44c); mov %psr, %l0; nop
305 mov (lev), %l3; b _C_LABEL(sparc_interrupt4m); mov %psr, %l0; nop
310 mov (lev), %l3; mov (bit), %l4; b softintr_sun44c; mov %psr, %l0
333 #define SYSCALL b _C_LABEL(_syscall); mov %psr, %l0; nop; nop
334 #define WINDOW_OF b window_of; mov %psr, %l0; nop; nop
335 #define WINDOW_UF b window_uf; mov %psr, %l0; nop; nop
337 #define ZS_INTERRUPT b zshard; mov %psr, %l0; nop; nop
368 TRAP(T_FPDISABLED) ! 04 = fp instr, but EF bit off in psr
400 TRAP(T_CPDISABLED) ! 24 = coprocessor instr, EC bit off in psr
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H A Dtrap.c222 trap(unsigned type, int psr, int pc, struct trapframe *tf) in trap() argument
241 if (psr & PSR_PS) { in trap()
297 snprintb(bits, sizeof(bits), PSR_BITS, psr); in trap()
335 snprintb(bits, sizeof(bits), PSR_BITS, psr); in trap()
759 mem_access_fault(unsigned type, int ser, u_int v, int pc, int psr, in mem_access_fault() argument
826 if (psr & PSR_PS) { in mem_access_fault()
922 if (psr & PSR_PS) { in mem_access_fault()
965 if ((psr & PSR_PS) == 0) { in mem_access_fault()
978 int pc, psr; in mem_access_fault4m() local
1013 psr = tf->tf_psr; in mem_access_fault4m()
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/netbsd-src/external/gpl3/gdb/dist/sim/testsuite/cr16/
H A Dtbit.cgs11 lpr r1, psr
14 spr psr, r1
22 lpr r1, psr
26 spr psr, r1
H A Dtbitb.cgs11 lpr r1, psr
14 spr psr, r1
22 lpr r1, psr
25 spr psr, r1
H A Dtbitw.cgs11 lpr r1, psr
13 spr psr, r1
21 lpr r1, psr
25 spr psr, r1
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
H A Ddmub_psr.c195 static void dmub_psr_construct(struct dmub_psr *psr, struct dc_context *ctx) in dmub_psr_construct() argument
197 psr->ctx = ctx; in dmub_psr_construct()
198 psr->funcs = &psr_funcs; in dmub_psr_construct()
206 struct dmub_psr *psr = kzalloc(sizeof(struct dmub_psr), GFP_KERNEL); in dmub_psr_create() local
208 if (psr == NULL) { in dmub_psr_create()
213 dmub_psr_construct(psr, ctx); in dmub_psr_create()
215 return psr; in dmub_psr_create()
/netbsd-src/sys/arch/arm/include/
H A Dlocore.h123 #define VALID_PSR(psr) \ argument
124 (((psr) & PSR_MODE) == PSR_USR32_MODE && ((psr) & I32_bit) == 0)
126 #define VALID_PSR(psr) \ argument
127 (((psr) & PSR_MODE) == PSR_USR32_MODE && ((psr) & IF32_bits) == 0)
/netbsd-src/sys/arch/sparc/stand/common/
H A Dsrt0.S94 wr %g0, 0, %wim ! make sure we can set psr
96 wr %g0, PSR_S|PSR_PS|PSR_PIL, %psr ! set initial psr
100 rd %psr, %l0
101 wr %l0, PSR_ET, %psr
134 rd %psr, %o0
136 wr %o0, 0xb00, %psr ! (11 << 8)
/netbsd-src/sys/arch/ia64/stand/ia64/ski/
H A Dssc.c49 register u_int64_t psr; in ssc() local
52 __asm __volatile("mov %0=psr;;" : "=r"(psr)); in ssc()
57 __asm __volatile("mov psr.l=%0;; srlz.d" :: "r"(psr)); in ssc()
/netbsd-src/external/gpl3/gcc/dist/gcc/d/dmd/
H A Descape.d287 ScopeRef psr; in checkParamArgumentEscape() local
289 psr = buildScopeRef(par.storageClass); in checkParamArgumentEscape()
291 psr = ScopeRef.None; in checkParamArgumentEscape()
366 if (psr == ScopeRef.Scope || in checkParamArgumentEscape()
367 psr == ScopeRef.RefScope || in checkParamArgumentEscape()
368 psr == ScopeRef.ReturnRef_Scope) in checkParamArgumentEscape()
1713 ScopeRef psr = buildScopeRef(stc); in visit() local
1714 if (psr == ScopeRef.ReturnScope || psr == ScopeRef.Ref_ReturnScope) in visit()
1716 else if (psr == ScopeRef.ReturnRef || psr == ScopeRef.ReturnRef_Scope) in visit()
1768 const psr = buildScopeRef(getThisStorageClass(fd)); in visit() local
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/netbsd-src/sys/arch/ia64/include/
H A Ddb_machdep.h56 ((db_addr_t)(regs)->tf_special.iip + (((regs)->tf_special.psr>>41) & 3))
60 #define PC_REGS(regs) ((db_addr_t)(regs)->tf_special.iip + (((regs)->tf_special.psr>>41) & 3))
63 #define db_set_single_step(regs) ((regs)->tf_special.psr |= IA64_PSR_SS)
64 #define db_clear_single_step(regs) ((regs)->tf_special.psr &= ~IA64_PSR_SS)

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