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Searched refs:port_clock (Results 1 – 19 of 19) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/i915/display/
H A Dintel_ddi.c1072 int clock = crtc_state->port_clock; in icl_pll_to_ddi_clk_sel()
1531 dotclock = intel_dotclock_calculate(pipe_config->port_clock, in ddi_dotclock_get()
1534 dotclock = intel_dotclock_calculate(pipe_config->port_clock, in ddi_dotclock_get()
1537 dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp; in ddi_dotclock_get()
1539 dotclock = pipe_config->port_clock; in ddi_dotclock_get()
1572 pipe_config->port_clock = link_clock; in icl_ddi_clock_get()
1621 pipe_config->port_clock = link_clock; in cnl_ddi_clock_get()
1668 pipe_config->port_clock = link_clock; in skl_ddi_clock_get()
1715 pipe_config->port_clock = link_clock * 2; in hsw_ddi_clock_get()
1738 pipe_config->port_clock = in bxt_ddi_clock_get()
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H A Dintel_dpll_mgr.c830 hsw_ddi_calculate_wrpll(crtc_state->port_clock * 1000, &r2, &n2, &p); in hsw_ddi_hdmi_get_dpll()
855 int clock = crtc_state->port_clock; in hsw_ddi_dp_get_dpll()
896 if (WARN_ON(crtc_state->port_clock / 2 != 135000)) in hsw_get_dpll()
1383 if (!skl_ddi_calculate_wrpll(crtc_state->port_clock * 1000, in skl_ddi_hdmi_pll_dividers()
1416 switch (crtc_state->port_clock / 2) { in skl_ddi_dp_set_dpll_hw_state()
1771 crtc_state->port_clock, in bxt_ddi_hdmi_pll_dividers()
1792 int clock = crtc_state->port_clock; in bxt_ddi_dp_pll_dividers()
1810 int clock = crtc_state->port_clock; in bxt_ddi_set_dpll_hw_state()
2285 u32 afe_clock = crtc_state->port_clock * 5; in cnl_ddi_calculate_wrpll()
2361 switch (crtc_state->port_clock / 2) { in cnl_ddi_dp_set_dpll_hw_state()
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H A Dintel_dpio_phy.c903 if (crtc_state->port_clock > 270000) in chv_phy_pre_encoder_enable()
905 else if (crtc_state->port_clock > 135000) in chv_phy_pre_encoder_enable()
907 else if (crtc_state->port_clock > 67500) in chv_phy_pre_encoder_enable()
909 else if (crtc_state->port_clock > 33750) in chv_phy_pre_encoder_enable()
H A Dintel_dp.c1815 if (pipe_config->port_clock == divisor[i].clock) { in intel_dp_set_clock()
1883 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, in intel_dp_compute_rate() argument
1890 intel_dp_rate_select(intel_dp, port_clock); in intel_dp_compute_rate()
1892 *link_bw = drm_dp_link_rate_to_bw_code(port_clock); in intel_dp_compute_rate()
2033 pipe_config->port_clock = link_clock; in intel_dp_compute_link_config_wide()
2155 pipe_config->port_clock = intel_dp->common_rates[limits->max_clock]; in intel_dp_dsc_compute_config()
2171 pipe_config->port_clock, in intel_dp_dsc_compute_config()
2292 pipe_config->lane_count, pipe_config->port_clock, in intel_dp_compute_link_config()
2299 intel_dp_max_data_rate(pipe_config->port_clock, in intel_dp_compute_link_config()
2303 pipe_config->lane_count, pipe_config->port_clock, in intel_dp_compute_link_config()
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H A Dintel_dp.h106 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
H A Dintel_audio.c135 crtc_state->port_clock == dp_aud_n_m[i].clock) in audio_config_dp_get_n_m()
282 crtc_state->port_clock == hdmi_ncts_table[i].clock) { in audio_config_hdmi_get_n()
742 crtc_state->port_clock, in intel_audio_codec_enable()
H A Dintel_dp_mst.c63 crtc_state->port_clock = limits->max_clock; in intel_dp_mst_compute_link_config()
88 crtc_state->port_clock, in intel_dp_mst_compute_link_config()
H A Dintel_crt.c142 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock; in intel_crt_get_config()
430 pipe_config->port_clock = 135000 * 2; in hsw_crt_compute_config()
H A Dintel_hdmi.c1841 dotclock = pipe_config->port_clock * 2 / 3; in intel_hdmi_get_config()
1843 dotclock = pipe_config->port_clock; in intel_hdmi_get_config()
2358 crtc_state->port_clock = intel_hdmi_port_clock(clock, bpc); in intel_hdmi_compute_clock()
2371 if (hdmi_port_clock_valid(intel_hdmi, crtc_state->port_clock, in intel_hdmi_compute_clock()
2374 crtc_state->port_clock); in intel_hdmi_compute_clock()
2472 if (pipe_config->port_clock > 340000) { in intel_hdmi_compute_config()
H A Dintel_lspcon.c201 crtc_state->port_clock /= 2; in lspcon_ycbcr420_config()
H A Dintel_dvo.c188 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock; in intel_dvo_get_config()
H A Dintel_display.c255 return pipe_config->port_clock; /* SPLL */ in intel_fdi_link_freq()
1045 crtc_state->port_clock, refclk, in bxt_find_best_dpll()
8277 if (pipe_config->port_clock == 162000 || in vlv_prepare_pll()
8858 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in i8xx_crtc_compute_clock()
8900 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in g4x_crtc_compute_clock()
8934 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in pnv_crtc_compute_clock()
8968 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in i9xx_crtc_compute_clock()
8989 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in chv_crtc_compute_clock()
9010 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in vlv_crtc_compute_clock()
9080 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); in vlv_crtc_clock_get()
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H A Dintel_cdclk.c1963 crtc_state->port_clock >= 540000 && in intel_crtc_compute_min_cdclk()
1990 min_cdclk = max(crtc_state->port_clock, min_cdclk); in intel_crtc_compute_min_cdclk()
2200 switch (crtc_state->port_clock / 2) { in skl_dpll0_vco()
H A Dintel_tv.c1123 tv_mode.clock = pipe_config->port_clock; in intel_tv_get_config()
1211 pipe_config->port_clock = tv_mode->clock; in intel_tv_compute_config()
H A Dicl_dsi.c1326 pipe_config->port_clock = in gen11_dsi_get_config()
1415 pipe_config->port_clock = afe_clk(encoder, pipe_config) / 5; in gen11_dsi_compute_config()
H A Dintel_display_types.h938 int port_clock; member
H A Dintel_lvds.c156 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock; in intel_lvds_get_config()
H A Dintel_sdvo.c1249 unsigned dotclock = pipe_config->port_clock; in i9xx_adjust_sdvo_tv_clock()
1652 dotclock = pipe_config->port_clock; in intel_sdvo_get_config()
H A Dvlv_dsi.c1212 pipe_config->port_clock = pclk; in intel_dsi_get_config()