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Searched refs:pix_clk_params (Results 1 – 13 of 13) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
H A Damdgpu_dce_clock_source.c402 struct pixel_clk_params *pix_clk_params, in pll_adjust_pix_clk() argument
410 switch (pix_clk_params->signal_type) { in pll_adjust_pix_clk()
412 requested_clk_100hz = pix_clk_params->requested_pix_clk_100hz; in pll_adjust_pix_clk()
413 if (pix_clk_params->pixel_encoding != PIXEL_ENCODING_YCBCR422) { in pll_adjust_pix_clk()
414 switch (pix_clk_params->color_depth) { in pll_adjust_pix_clk()
435 requested_clk_100hz = pix_clk_params->requested_sym_clk * 10; in pll_adjust_pix_clk()
436 actual_pix_clk_100hz = pix_clk_params->requested_pix_clk_100hz; in pll_adjust_pix_clk()
440 requested_clk_100hz = pix_clk_params->requested_pix_clk_100hz; in pll_adjust_pix_clk()
441 actual_pix_clk_100hz = pix_clk_params->requested_pix_clk_100hz; in pll_adjust_pix_clk()
447 encoder_object_id = pix_clk_params->encoder_object_id; in pll_adjust_pix_clk()
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H A Ddce_clk_mgr.c204 if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10 > max_pix_clk) in get_max_pixel_clock_for_all_paths()
205 max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10; in get_max_pixel_clock_for_all_paths()
211 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk > max_pix_clk) in get_max_pixel_clock_for_all_paths()
212 max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_sym_clk; in get_max_pixel_clock_for_all_paths()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce100/
H A Damdgpu_dce_clk_mgr.c185 if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10 > max_pix_clk) in dce_get_max_pixel_clock_for_all_paths()
186 max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10; in dce_get_max_pixel_clock_for_all_paths()
192 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk > max_pix_clk) in dce_get_max_pixel_clock_for_all_paths()
193 max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_sym_clk; in dce_get_max_pixel_clock_for_all_paths()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/
H A Damdgpu_dc_link_hwss.c121 pipes[i].stream_res.pix_clk_params.requested_pix_clk_100hz = in dp_enable_link_phy()
125 &pipes[i].stream_res.pix_clk_params, in dp_enable_link_phy()
H A Damdgpu_dc_link.c1518 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk = in enable_link_dp()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/
H A Dcore_types.h237 struct pixel_clk_params pix_clk_params; member
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/
H A Damdgpu_dce110_hw_sequencer.c1154 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz; in build_audio_output()
1157 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz; in build_audio_output()
1163 if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) { in build_audio_output()
1167 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz/2; in build_audio_output()
1297 &pipe_ctx->stream_res.pix_clk_params, in dce110_enable_stream_timing()
H A Damdgpu_dce110_resource.c897 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); in dce110_resource_build_pipe_hw_param()
900 &pipe_ctx->stream_res.pix_clk_params, in dce110_resource_build_pipe_hw_param()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
H A Damdgpu_dcn10_resource.c1067 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); in build_pipe_hw_param()
1071 &pipe_ctx->stream_res.pix_clk_params, in build_pipe_hw_param()
H A Damdgpu_dcn10_hw_sequencer_debug.c437 …pix_clk = dc->current_state->res_ctx.pipe_ctx[i].stream_res.pix_clk_params.requested_pix_clk_100hz… in dcn10_get_otg_states()
H A Damdgpu_dcn10_hw_sequencer.c802 &pipe_ctx->stream_res.pix_clk_params, in dcn10_enable_stream_timing()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
H A Damdgpu_dcn20_resource.c1491 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); in build_pipe_hw_param()
1495 &pipe_ctx->stream_res.pix_clk_params, in build_pipe_hw_param()
H A Damdgpu_dcn20_hwseq.c647 &pipe_ctx->stream_res.pix_clk_params, in dcn20_enable_stream_timing()