| /netbsd-src/sys/arch/powerpc/ibm4xx/dev/ |
| H A D | gpio_opb.c | 127 const uint32_t pin_mask = 1 << GPIO_PIN_SHIFT(i + 1); in gpio_opb_attach() local
135 (reg_odr & pin_mask) in gpio_opb_attach()
137 : ((reg_tcr & pin_mask) in gpio_opb_attach()
140 pin->pin_state = (reg_ir & pin_mask) != 0; in gpio_opb_attach()
173 const uint32_t pin_mask = 1 << GPIO_PIN_SHIFT(p); in gpio_opb_pin_write() local
176 gpio_clear(sc, GPIO_OR, pin_mask); in gpio_opb_pin_write()
178 gpio_set(sc, GPIO_OR, pin_mask); in gpio_opb_pin_write()
187 const uint32_t pin_mask = 1 << GPIO_PIN_SHIFT(p); in gpio_opb_pin_ctl() local
191 gpio_clear(sc, GPIO_ODR, pin_mask); in gpio_opb_pin_ctl()
194 gpio_set(sc, GPIO_TCR, pin_mask); in gpio_opb_pin_ctl()
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| /netbsd-src/sys/arch/arm/ti/ |
| H A D | ti_gpio.c | 268 const uint32_t pin_mask = __BIT(pin); in ti_gpio_intr_disable() local
274 WR4(sc, GPIO_IRQENABLE1, val & ~pin_mask); in ti_gpio_intr_disable()
276 WR4(sc, GPIO_IRQENABLE1_CLR, pin_mask); in ti_gpio_intr_disable()
319 const uint32_t pin_mask = __BIT(pin); in ti_gpio_intr_establish() local
324 val |= pin_mask; in ti_gpio_intr_establish()
326 val &= ~pin_mask; in ti_gpio_intr_establish()
331 val |= pin_mask; in ti_gpio_intr_establish()
333 val &= ~pin_mask; in ti_gpio_intr_establish()
338 val |= pin_mask; in ti_gpio_intr_establish()
340 val &= ~pin_mask; in ti_gpio_intr_establish()
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/i915/ |
| H A D | i915_irq.c | 1160 u32 *pin_mask, u32 *long_mask, in intel_get_hpd_pins() argument
1167 BUILD_BUG_ON(BITS_PER_TYPE(*pin_mask) < HPD_NUM_PINS); in intel_get_hpd_pins()
1173 *pin_mask |= BIT(pin); in intel_get_hpd_pins()
1180 hotplug_trigger, dig_hotplug_reg, *pin_mask, *long_mask); in intel_get_hpd_pins()
1495 u32 pin_mask = 0, long_mask = 0; in i9xx_hpd_irq_handler() local
1502 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, in i9xx_hpd_irq_handler()
1507 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); in i9xx_hpd_irq_handler()
1516 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, in i9xx_hpd_irq_handler()
1520 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); in i9xx_hpd_irq_handler()
1694 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; in ibx_hpd_irq_handler() local
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/nouveau/dispnv04/ |
| H A D | nouveau_dispnv04_tvnv17.c | 135 get_tv_detect_quirks(struct drm_device *dev, uint32_t *pin_mask) in get_tv_detect_quirks() argument
141 *pin_mask = device->quirk->tv_pin_mask; in get_tv_detect_quirks()
156 bool reliable = get_tv_detect_quirks(dev, &tv_enc->pin_mask); in nv17_tv_detect()
164 tv_enc->pin_mask = in nv17_tv_detect()
167 tv_enc->pin_mask = in nv17_tv_detect()
171 switch (tv_enc->pin_mask) { in nv17_tv_detect()
809 tv_enc->pin_mask = 0; in nv17_tv_create()
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| H A D | tvnv17.h | 85 uint32_t pin_mask; member
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| H A D | nouveau_dispnv04_tvmodesnv17.c | 492 if (tv_enc->pin_mask & 0x4) in nv17_tv_update_properties()
494 else if (tv_enc->pin_mask & 0x2) in nv17_tv_update_properties()
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| H A D | intel_tc.c | 81 u32 pin_mask; in intel_tc_port_get_pin_assignment_mask() local
83 pin_mask = intel_uncore_read(uncore, in intel_tc_port_get_pin_assignment_mask()
86 WARN_ON(pin_mask == 0xffffffff); in intel_tc_port_get_pin_assignment_mask()
88 return (pin_mask & DP_PIN_ASSIGNMENT_MASK(dig_port->tc_phy_fia_idx)) >> in intel_tc_port_get_pin_assignment_mask()
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| H A D | intel_hotplug.c | 455 u32 pin_mask, u32 long_mask) in intel_hpd_irq_handler() argument
464 if (!pin_mask) in intel_hpd_irq_handler()
481 if (!(BIT(pin) & pin_mask)) in intel_hpd_irq_handler()
507 if (!(BIT(pin) & pin_mask)) in intel_hpd_irq_handler()
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| H A D | intel_hotplug.h | 25 u32 pin_mask, u32 long_mask);
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