Searched refs:performance_levels (Results 1 – 12 of 12) sorted by relevance
814 if (ps->performance_levels[i].mclk > max_limits->mclk) in ni_apply_state_adjust_rules()815 ps->performance_levels[i].mclk = max_limits->mclk; in ni_apply_state_adjust_rules()816 if (ps->performance_levels[i].sclk > max_limits->sclk) in ni_apply_state_adjust_rules()817 ps->performance_levels[i].sclk = max_limits->sclk; in ni_apply_state_adjust_rules()818 if (ps->performance_levels[i].vddc > max_limits->vddc) in ni_apply_state_adjust_rules()819 ps->performance_levels[i].vddc = max_limits->vddc; in ni_apply_state_adjust_rules()820 if (ps->performance_levels[i].vddci > max_limits->vddci) in ni_apply_state_adjust_rules()821 ps->performance_levels[i].vddci = max_limits->vddci; in ni_apply_state_adjust_rules()829 ps->performance_levels[0].mclk = in ni_apply_state_adjust_rules()830 ps->performance_levels[ps->performance_level_count - 1].mclk; in ni_apply_state_adjust_rules()[all …]
2329 prev_sclk = state->performance_levels[i-1].sclk; in si_populate_power_containment_values()2330 max_sclk = state->performance_levels[i].sclk; in si_populate_power_containment_values()2349 if (min_sclk < state->performance_levels[0].sclk) in si_populate_power_containment_values()2350 min_sclk = state->performance_levels[0].sclk; in si_populate_power_containment_values()2356 state->performance_levels[i-1].vddc, &vddc); in si_populate_power_containment_values()2365 state->performance_levels[i].vddc, &vddc); in si_populate_power_containment_values()2424 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) && in si_populate_sq_ramping_values()3036 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc) in si_apply_state_adjust_rules()3037 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc; in si_apply_state_adjust_rules()3041 if (ps->performance_levels[i].mclk > max_limits->mclk) in si_apply_state_adjust_rules()[all …]
835 if (ps->performance_levels[i].mclk > max_limits->mclk) in ci_apply_state_adjust_rules()836 ps->performance_levels[i].mclk = max_limits->mclk; in ci_apply_state_adjust_rules()837 if (ps->performance_levels[i].sclk > max_limits->sclk) in ci_apply_state_adjust_rules()838 ps->performance_levels[i].sclk = max_limits->sclk; in ci_apply_state_adjust_rules()845 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; in ci_apply_state_adjust_rules()846 sclk = ps->performance_levels[0].sclk; in ci_apply_state_adjust_rules()848 mclk = ps->performance_levels[0].mclk; in ci_apply_state_adjust_rules()849 sclk = ps->performance_levels[0].sclk; in ci_apply_state_adjust_rules()859 ps->performance_levels[0].sclk = sclk; in ci_apply_state_adjust_rules()860 ps->performance_levels[0].mclk = mclk; in ci_apply_state_adjust_rules()[all …]
177 struct rv7xx_pl performance_levels[NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE]; member
52 struct ci_pl performance_levels[CISLANDS_MAX_HARDWARE_POWERLEVELS]; member
2924 if (smu7_ps->performance_levels[i].memory_clock > max_limits->mclk) in smu7_apply_state_adjust_rules()2925 smu7_ps->performance_levels[i].memory_clock = max_limits->mclk; in smu7_apply_state_adjust_rules()2926 if (smu7_ps->performance_levels[i].engine_clock > max_limits->sclk) in smu7_apply_state_adjust_rules()2927 smu7_ps->performance_levels[i].engine_clock = max_limits->sclk; in smu7_apply_state_adjust_rules()2971 sclk = smu7_ps->performance_levels[0].engine_clock; in smu7_apply_state_adjust_rules()2972 mclk = smu7_ps->performance_levels[0].memory_clock; in smu7_apply_state_adjust_rules()2975 mclk = smu7_ps->performance_levels in smu7_apply_state_adjust_rules()2986 smu7_ps->performance_levels[0].engine_clock = sclk; in smu7_apply_state_adjust_rules()2987 smu7_ps->performance_levels[0].memory_clock = mclk; in smu7_apply_state_adjust_rules()2989 smu7_ps->performance_levels[1].engine_clock = in smu7_apply_state_adjust_rules()[all …]
3084 performance_level = &(vega10_power_state->performance_levels in vega10_get_pp_table_entry_callback_func()3108 performance_level = &(vega10_power_state->performance_levels in vega10_get_pp_table_entry_callback_func()3206 if (vega10_ps->performance_levels[i].mem_clock > in vega10_apply_state_adjust_rules()3208 vega10_ps->performance_levels[i].mem_clock = in vega10_apply_state_adjust_rules()3210 if (vega10_ps->performance_levels[i].gfx_clock > in vega10_apply_state_adjust_rules()3212 vega10_ps->performance_levels[i].gfx_clock = in vega10_apply_state_adjust_rules()3268 sclk = vega10_ps->performance_levels[0].gfx_clock; in vega10_apply_state_adjust_rules()3269 mclk = vega10_ps->performance_levels[0].mem_clock; in vega10_apply_state_adjust_rules()3279 vega10_ps->performance_levels[0].gfx_clock = sclk; in vega10_apply_state_adjust_rules()3280 vega10_ps->performance_levels[0].mem_clock = mclk; in vega10_apply_state_adjust_rules()[all …]
87 struct smu7_performance_level performance_levels[SMU7_MAX_HARDWARE_POWERLEVELS]; member
114 struct vega10_performance_level performance_levels[VEGA10_MAX_HARDWARE_POWERLEVELS]; member
131 struct vega20_performance_level performance_levels[VEGA20_MAX_HARDWARE_POWERLEVELS]; member
2427 prev_sclk = state->performance_levels[i-1].sclk; in si_populate_power_containment_values()2428 max_sclk = state->performance_levels[i].sclk; in si_populate_power_containment_values()2446 if (min_sclk < state->performance_levels[0].sclk) in si_populate_power_containment_values()2447 min_sclk = state->performance_levels[0].sclk; in si_populate_power_containment_values()2453 state->performance_levels[i-1].vddc, &vddc); in si_populate_power_containment_values()2462 state->performance_levels[i].vddc, &vddc); in si_populate_power_containment_values()2521 if ((state->performance_levels[i].sclk >= adev->pm.dpm.sq_ramping_threshold) && in si_populate_sq_ramping_values()3188 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk >= in ni_set_uvd_clock_before_set_eng_clock()3189 current_state->performance_levels[current_state->performance_level_count - 1].sclk) in ni_set_uvd_clock_before_set_eng_clock()3206 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk < in ni_set_uvd_clock_after_set_eng_clock()[all …]
619 struct rv7xx_pl performance_levels[NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE]; member