Home
last modified time | relevance | path

Searched refs:od_table (Results 1 – 4 of 4) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/
H A Damdgpu_navi10_ppt.c748 static inline bool navi10_od_feature_is_supported(struct smu_11_0_overdrive_table *od_table, enum S… in navi10_od_feature_is_supported() argument
750 return od_table->cap[cap]; in navi10_od_feature_is_supported()
753 static void navi10_od_setting_get_range(struct smu_11_0_overdrive_table *od_table, in navi10_od_setting_get_range() argument
758 *min = od_table->min[setting]; in navi10_od_setting_get_range()
760 *max = od_table->max[setting]; in navi10_od_setting_get_range()
777 OverDriveTable_t *od_table = in navi10_print_clk_levels() local
856 if (!smu->od_enabled || !od_table || !od_settings) in navi10_print_clk_levels()
861 size += sprintf(buf + size, "0: %uMhz\n1: %uMhz\n", od_table->GfxclkFmin, od_table->GfxclkFmax); in navi10_print_clk_levels()
864 if (!smu->od_enabled || !od_table || !od_settings) in navi10_print_clk_levels()
869 size += sprintf(buf + size, "1: %uMHz\n", od_table->UclkFmax); in navi10_print_clk_levels()
[all …]
H A Damdgpu_vega20_ppt.c964 OverDriveTable_t *od_table = in vega20_print_clk_levels() local
1099 od_table->GfxclkFmin); in vega20_print_clk_levels()
1101 od_table->GfxclkFmax); in vega20_print_clk_levels()
1110 od_table->UclkFmax); in vega20_print_clk_levels()
1124 od_table->GfxclkFreq1, in vega20_print_clk_levels()
1125 od_table->GfxclkVolt1 / VOLTAGE_SCALE); in vega20_print_clk_levels()
1127 od_table->GfxclkFreq2, in vega20_print_clk_levels()
1128 od_table->GfxclkVolt2 / VOLTAGE_SCALE); in vega20_print_clk_levels()
1130 od_table->GfxclkFreq3, in vega20_print_clk_levels()
1131 od_table->GfxclkVolt3 / VOLTAGE_SCALE); in vega20_print_clk_levels()
[all …]
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
H A Damdgpu_vega20_hwmgr.c1226 OverDriveTable_t *od_table = &(data->smc_state_table.overdrive_table); in vega20_od8_initialize_default_settings() local
1236 ret = smum_smc_table_manager(hwmgr, (uint8_t *)od_table, TABLE_OVERDRIVE, true); in vega20_od8_initialize_default_settings()
1243 od_table->GfxclkFmin; in vega20_od8_initialize_default_settings()
1245 od_table->GfxclkFmax; in vega20_od8_initialize_default_settings()
1254 od_table->GfxclkFreq1 = od_table->GfxclkFmin; in vega20_od8_initialize_default_settings()
1256 od_table->GfxclkFreq1; in vega20_od8_initialize_default_settings()
1258 od_table->GfxclkFreq3 = od_table->GfxclkFmax; in vega20_od8_initialize_default_settings()
1260 od_table->GfxclkFreq3; in vega20_od8_initialize_default_settings()
1262 od_table->GfxclkFreq2 = (od_table->GfxclkFreq1 + od_table->GfxclkFreq3) / 2; in vega20_od8_initialize_default_settings()
1264 od_table->GfxclkFreq2; in vega20_od8_initialize_default_settings()
[all …]
H A Damdgpu_vega10_hwmgr.c317 struct phm_ppt_v1_clock_voltage_dependency_table *od_table[3]; in vega10_odn_initial_default_setting() local
339 od_table[0] = (struct phm_ppt_v1_clock_voltage_dependency_table *)&odn_table->vdd_dep_on_sclk; in vega10_odn_initial_default_setting()
340 od_table[1] = (struct phm_ppt_v1_clock_voltage_dependency_table *)&odn_table->vdd_dep_on_mclk; in vega10_odn_initial_default_setting()
341 od_table[2] = (struct phm_ppt_v1_clock_voltage_dependency_table *)&odn_table->vdd_dep_on_socclk; in vega10_odn_initial_default_setting()
344 smu_get_voltage_dependency_table_ppt_v1(dep_table[i], od_table[i]); in vega10_odn_initial_default_setting()
351 i = od_table[2]->count - 1; in vega10_odn_initial_default_setting()
352 …od_table[2]->entries[i].clk = hwmgr->platform_descriptor.overdriveLimit.memoryClock > od_table[2]-… in vega10_odn_initial_default_setting()
354 od_table[2]->entries[i].clk; in vega10_odn_initial_default_setting()
355 od_table[2]->entries[i].vddc = odn_table->max_vddc > od_table[2]->entries[i].vddc ? in vega10_odn_initial_default_setting()
357 od_table[2]->entries[i].vddc; in vega10_odn_initial_default_setting()