Searched refs:nv_funcs (Results 1 – 4 of 4) sorted by relevance
1004 funcs->nv_funcs.pp_smu.dm = ctx; in dm_pp_get_funcs()1005 funcs->nv_funcs.set_display_count = pp_nv_set_display_count; in dm_pp_get_funcs()1006 funcs->nv_funcs.set_hard_min_dcfclk_by_freq = in dm_pp_get_funcs()1008 funcs->nv_funcs.set_min_deep_sleep_dcfclk = in dm_pp_get_funcs()1010 funcs->nv_funcs.set_voltage_by_freq = in dm_pp_get_funcs()1012 funcs->nv_funcs.set_wm_ranges = pp_nv_set_wm_ranges; in dm_pp_get_funcs()1015 funcs->nv_funcs.set_pme_wa_enable = NULL; in dm_pp_get_funcs()1017 funcs->nv_funcs.set_hard_min_uclk_by_freq = pp_nv_set_hard_min_uclk_by_freq; in dm_pp_get_funcs()1019 funcs->nv_funcs.get_maximum_sustainable_clocks = pp_nv_get_maximum_sustainable_clocks; in dm_pp_get_funcs()1021 funcs->nv_funcs.get_uclk_dpm_states = pp_nv_get_uclk_dpm_states; in dm_pp_get_funcs()[all …]
288 struct pp_smu_funcs_nv nv_funcs; member
181 pp_smu = &dc->res_pool->pp_smu->nv_funcs; in dcn2_update_clocks()348 pp_smu = &clk_mgr->pp_smu->nv_funcs; in dcn2_enable_pme_wa()
3453 if (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) { in init_soc_bounding_box()3454 status = (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) in init_soc_bounding_box()3455 (&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states); in init_soc_bounding_box()3460 if (pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) { in init_soc_bounding_box()3461 status = (*pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) in init_soc_bounding_box()3462 (&pool->base.pp_smu->nv_funcs.pp_smu, &max_clocks); in init_soc_bounding_box()3664 if (pool->base.pp_smu->nv_funcs.set_wm_ranges) in dcn20_resource_construct()3665 pool->base.pp_smu->nv_funcs.set_wm_ranges(&pool->base.pp_smu->nv_funcs.pp_smu, &ranges); in dcn20_resource_construct()