Searched refs:num_wm_dmif_sets (Results 1 – 6 of 6) sorted by relevance
560 wm_with_clock_ranges.num_wm_dmif_sets = ranges->num_reader_wm_sets; in pp_rv_set_wm_ranges()563 for (i = 0; i < wm_with_clock_ranges.num_wm_dmif_sets; i++) { in pp_rv_set_wm_ranges()680 wm_with_clock_ranges.num_wm_dmif_sets = ranges->num_reader_wm_sets; in pp_nv_set_wm_ranges()683 for (i = 0; i < wm_with_clock_ranges.num_wm_dmif_sets; i++) { in pp_nv_set_wm_ranges()935 wm_with_clock_ranges.num_wm_dmif_sets = ranges->num_reader_wm_sets; in pp_rn_set_wm_ranges()938 for (i = 0; i < wm_with_clock_ranges.num_wm_dmif_sets; i++) { in pp_rn_set_wm_ranges()
176 uint32_t num_wm_dmif_sets; member
718 if (wm_with_clock_ranges->num_wm_dmif_sets > 4 || wm_with_clock_ranges->num_wm_mcif_sets > 4) in smu_set_watermarks_for_clocks_ranges()721 for (i = 0; i < wm_with_clock_ranges->num_wm_dmif_sets; i++) { in smu_set_watermarks_for_clocks_ranges()
777 if (clock_ranges->num_wm_dmif_sets > 4 || in renoir_set_watermarks_table()782 for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) { in renoir_set_watermarks_table()
1510 if (clock_ranges->num_wm_dmif_sets > 4 || in navi10_set_watermarks_table()1514 for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) { in navi10_set_watermarks_table()
3053 if (clock_ranges->num_wm_dmif_sets > 4 || in vega20_set_watermarks_table()3057 for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) { in vega20_set_watermarks_table()