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Searched refs:num_slices_h (Results 1 – 8 of 8) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dsc/
H A Damdgpu_dc_dsc.c571 int num_slices_h; in setup_dsc_config() local
709 num_slices_h = min_slices_h; in setup_dsc_config()
712 num_slices_h = min(policy.max_slices_h, max_slices_h); in setup_dsc_config()
714 num_slices_h = max_slices_h; in setup_dsc_config()
720 num_slices_h = min(policy.max_slices_h, max_slices_h); in setup_dsc_config()
722 num_slices_h = max_slices_h; in setup_dsc_config()
724 num_slices_h = min_slices_h; in setup_dsc_config()
732 dsc_cfg->num_slices_h = num_slices_h; in setup_dsc_config()
733 slice_width = pic_width / num_slices_h; in setup_dsc_config()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
H A Damdgpu_dcn20_dsc.c182 DC_LOG_DSC("\tnum_slices_h %d", config->dc_dsc_cfg.num_slices_h); in dsc_config_log()
339 ASSERT(dsc_cfg->dc_dsc_cfg.num_slices_h); in dsc_prepare_config()
351 if (!dsc_cfg->dc_dsc_cfg.num_slices_v || !dsc_cfg->dc_dsc_cfg.num_slices_h || in dsc_prepare_config()
368 dsc_reg_vals->num_slices_h = dsc_cfg->dc_dsc_cfg.num_slices_h; in dsc_prepare_config()
380 dsc_reg_vals->pps.slice_width = dsc_cfg->pic_width / dsc_cfg->dc_dsc_cfg.num_slices_h; in dsc_prepare_config()
539 reg_vals->ich_reset_at_eol = reg_vals->num_slices_h == 1 ? 0 : 0xf; in dsc_update_from_dsc_parameters()
565 NUMBER_OF_SLICES_PER_LINE, reg_vals->num_slices_h - 1, in dsc_write_to_registers()
H A Ddcn20_dsc.h546 uint32_t num_slices_h; member
H A Damdgpu_dcn20_resource.c1928 pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h; in dcn20_populate_dml_pipes_from_context()
2311 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; in dcn20_validate_dsc()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/
H A Damdgpu_dc_link_hwss.c438 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); in dp_set_dsc_on_stream()
439 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; in dp_set_dsc_on_stream()
449 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt; in dp_set_dsc_on_stream()
H A Damdgpu_dc_stream.c115 stream->timing.dsc_cfg.num_slices_h = 0; in dc_stream_construct()
H A Damdgpu_dc.c2018 uint32_t enable_dsc = (update->dsc_config->num_slices_h != 0 && in copy_stream_update_to_stream()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/
H A Ddc_hw_types.h705 uint32_t num_slices_h; /* Number of DSC slices - horizontal */ member