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/netbsd-src/sys/arch/evbmips/loongson/dev/
H A Dglx.c82 glx_msra2mbxa(uint msr) in glx_msra2mbxa() argument
84 uint rf = (msr & GLX_MSR_ADDR_RF); in glx_msra2mbxa()
85 return ((rf << GLX_MSR_ADDR_RF_SHIFT) | (msr & GLX_MSR_ADDR_TARGET)); in glx_msra2mbxa()
113 uint64_t msr; in glx_init() local
133 msr = rdmsr(GCSC_DIVIL_BALL_OPTS); /* 0x71 */ in glx_init()
134 wrmsr(GCSC_DIVIL_BALL_OPTS, msr | 0x01); in glx_init()
139 msr = 0; in glx_init()
140 msr |= 11 << 8; in glx_init()
141 msr |= 9 << 16; in glx_init()
142 wrmsr(GCSC_PIC_YSEL_LOW, msr); in glx_init()
[all …]
/netbsd-src/sys/arch/x86/x86/
H A Dintel_busclock.c50 uint64_t msr; in via_get_bus_clock() local
53 msr = rdmsr(MSR_EBL_CR_POWERON); in via_get_bus_clock()
54 bus = (msr >> 18) & 0x3; in via_get_bus_clock()
78 uint64_t msr; in viac7_get_bus_clock() local
81 msr = rdmsr(MSR_PERF_STATUS); in viac7_get_bus_clock()
82 mult = (msr >> 8) & 0xff; in viac7_get_bus_clock()
93 uint64_t msr; in p3_get_bus_clock() local
108 if (rdmsr_safe(MSR_FSB_FREQ, &msr) == EFAULT) { in p3_get_bus_clock()
113 bus = (msr >> 0) & 0x7; in p3_get_bus_clock()
125 if (rdmsr_safe(MSR_FSB_FREQ, &msr) == EFAULT) { in p3_get_bus_clock()
[all …]
H A Dcoretemp.c166 uint64_t msr; in coretemp_attach() local
171 msr = rdmsr(MSR_THERM_STATUS); in coretemp_attach()
172 msr = __SHIFTOUT(msr, MSR_THERM_STATUS_RESOLUTION); in coretemp_attach()
175 aprint_normal(": thermal sensor, %u C resolution", (uint32_t)msr); in coretemp_attach()
226 uint64_t msr; in coretemp_quirks() local
238 msr = rdmsr(MSR_THERM_STATUS); in coretemp_quirks()
240 if ((msr & MSR_THERM_STATUS_VALID) == 0) in coretemp_quirks()
252 msr = rdmsr(MSR_BIOS_SIGN); in coretemp_quirks()
253 msr = msr >> 32; in coretemp_quirks()
255 if (msr < 0x39) in coretemp_quirks()
[all …]
H A Dspectre.c123 uint64_t msr; in v2_detect_method() local
131 msr = rdmsr(MSR_IA32_ARCH_CAPABILITIES); in v2_detect_method()
132 if (msr & IA32_ARCH_IBRS_ALL) { in v2_detect_method()
240 uint64_t msr; in mitigation_v2_apply_cpu() local
259 msr = rdmsr(MSR_IA32_SPEC_CTRL); in mitigation_v2_apply_cpu()
261 msr |= IA32_SPEC_CTRL_IBRS; in mitigation_v2_apply_cpu()
263 msr &= ~IA32_SPEC_CTRL_IBRS; in mitigation_v2_apply_cpu()
265 wrmsr(MSR_IA32_SPEC_CTRL, msr); in mitigation_v2_apply_cpu()
268 msr = rdmsr(MSR_IC_CFG); in mitigation_v2_apply_cpu()
270 msr |= IC_CFG_DIS_IND; in mitigation_v2_apply_cpu()
[all …]
H A Dodcm.c329 uint64_t msr; in odcm_state_get() local
333 msr = rdmsr(MSR_THERM_CONTROL); in odcm_state_get()
335 if ((msr & ODCM_ENABLE) == 0) in odcm_state_get()
338 msr = (msr >> ODCM_REGOFFSET) & (ODCM_MAXSTATES - 1); in odcm_state_get()
342 KASSERT(msr < INT_MAX); in odcm_state_get()
344 if ((int)msr == state[i].reg) { in odcm_state_get()
358 struct msr_rw_info msr; in odcm_state_set() local
370 msr.msr_read = true; in odcm_state_set()
371 msr.msr_type = MSR_THERM_CONTROL; in odcm_state_set()
372 msr.msr_mask = 0x1e; in odcm_state_set()
[all …]
/netbsd-src/sys/arch/aarch64/aarch64/
H A Dlocore_el2.S74 msr hcr_el2, x2
78 msr vpidr_el2, x2
82 msr vmpidr_el2, x2
89 msr sctlr_el1, x2
95 msr cpacr_el1, x2
100 msr cptr_el2, x2
103 msr hstr_el2, xzr
108 msr cnthctl_el2, x2
111 msr cntvoff_el2, xzr
115 msr vbar_el2, x2
[all …]
H A Dcpuswitch.S93 msr cpacr_el1, x5 /* restore cpacr_el1 */
102 msr APIAKeyLo_EL1, x5
103 msr APIAKeyHi_EL1, x6
111 msr APIBKeyLo_EL1, x5
112 msr APIBKeyHi_EL1, x6
114 msr APDAKeyLo_EL1, x5
115 msr APDAKeyHi_EL1, x6
117 msr APDBKeyLo_EL1, x5
118 msr APDBKeyHi_EL1, x6
120 msr APGAKeyLo_EL1, x5
[all …]
H A Dvectors.S105 msr APIAKeyLo_EL1, x5
106 msr APIAKeyHi_EL1, x6
235 msr elr_el1, x0 /* exception pc */
236 msr spsr_el1, x1 /* exception pstate */
285 msr cpacr_el1, x23 /* FP unit EL0 handover */
289 msr tpidr_el0, x0
291 msr tpidrro_el0, x0
300 msr APIAKeyLo_EL1, x5
301 msr APIAKeyHi_EL1, x6
315 msr elr_el1, x0 /* exception pc */
[all …]
H A Dlocore.S163 msr vbar_el1, x0
173 msr tpidr_el0, xzr
174 msr tpidrro_el0, xzr
178 msr tpidr_el1, x0
196 msr sctlr_el1, x0
243 msr mdscr_el1, xzr
244 msr oslar_el1, xzr
247 msr contextidr_el1, xzr
250 msr cpacr_el1, xzr
256 msr cntkctl_el1, x0
[all …]
/netbsd-src/lib/libc/arch/powerpc/gen/
H A Dfpsetmask.c54 uint32_t msr; in __weak_alias() local
56 __asm volatile ("mfmsr %0" : "=r"(msr)); in __weak_alias()
57 return msr; in __weak_alias()
61 mtmsr(uint32_t msr) in mtmsr() argument
64 __asm volatile ("mtmsr %0" : : "r"(msr)); in mtmsr()
77 uint32_t msr; in fpsetmask() local
86 msr = mfmsr(); in fpsetmask()
87 msr = (msr & ~(PSL_FE0 | PSL_FE1)) | in fpsetmask()
89 mtmsr(msr); in fpsetmask()
/netbsd-src/sys/arch/powerpc/oea/
H A Daltivec.c87 const register_t msr = mfmsr(); in vec_state_load() local
88 mtmsr((msr & ~PSL_EE) | PSL_VEC); in vec_state_load()
100 mtmsr(msr); in vec_state_load()
124 const register_t msr = mfmsr(); in vec_state_save() local
125 mtmsr((msr & ~PSL_EE) | PSL_VEC); in vec_state_save()
147 mtmsr(msr); in vec_state_save()
216 register_t omsr, msr; in vzeropage() local
223 msr = (omsr & ~PSL_EE) | PSL_VEC; in vzeropage()
224 __asm volatile("sync; mtmsr %0; isync" :: "r"(msr)); in vzeropage()
253 :: [msr] "r"(msr), [pa] "b"(pa), [ea] "b"(ea), in vzeropage()
[all …]
/netbsd-src/sys/arch/powerpc/booke/
H A Dcopyout.c54 register_t msr; in copyout_uint8() local
60 : [msr] "=&r" (msr) in copyout_uint8()
67 register_t msr; in copyout_uint16() local
73 : [msr] "=&r" (msr) in copyout_uint16()
80 register_t msr; in copyout_uint32() local
86 : [msr] "=&r" (msr) in copyout_uint32()
94 register_t msr;
100 : [msr] "=&r" (msr)
108 register_t msr;
119 : [msr] "=&r" (msr), [tmp] "=&r" (tmp)
[all …]
H A Dcopyin.c54 register_t msr; in copyin_byte() local
61 : [msr] "=&r" (msr), [data] "=r" (data) in copyin_byte()
69 register_t msr; in copyin_halfword() local
76 : [msr] "=&r" (msr), [data] "=r" (data) in copyin_halfword()
84 register_t msr; in copyin_word() local
91 : [msr] "=&r" (msr), [data] "=r" (data) in copyin_word()
99 register_t msr; in copyin_word_bswap() local
106 : [msr] "=&r" (msr), [data] "=r" (data) in copyin_word_bswap()
114 register_t msr; in copyin_8words() local
128 : [msr] "=&r" (msr), in copyin_8words()
[all …]
/netbsd-src/sys/arch/powerpc/powerpc/
H A Dclock.c106 uint32_t msr; in cpu_initclocks()
123 : "=r"(msr) : "K"(PSL_EE|PSL_RI)); in cpu_initclocks()
142 const register_t msr = mfmsr(); in decr_intr()
184 mtmsr(msr | PSL_EE); in decr_intr()
192 mtmsr(msr); in decr_intr()
195 mtmsr(msr | PSL_EE); in decr_intr()
197 mtmsr(msr); in decr_intr()
260 int msr, scratch; in get_powerpc_timecount()
263 : "=r"(msr), "=r"(scratch) : "K"((u_short)~PSL_EE)); in get_powerpc_timecount()
266 mtmsr(msr);
105 uint32_t msr; cpu_initclocks() local
141 const register_t msr = mfmsr(); decr_intr() local
255 int msr, scratch; get_powerpc_timecount() local
271 int msr, scratch; get_601_timecount() local
[all...]
H A Dpmap_subr.c285 register_t msr = 0; /* XXX: gcc */ in pmap_zero_page() local
321 msr = MFMSR(); in pmap_zero_page()
322 MTMSR(msr & ~PSL_DR); in pmap_zero_page()
353 MTMSR(msr); in pmap_zero_page()
364 register_t msr; in pmap_copy_page() local
409 msr = MFMSR(); in pmap_copy_page()
410 MTMSR(msr & ~PSL_DR); in pmap_copy_page()
426 MTMSR(msr); in pmap_copy_page()
443 register_t msr; in pmap_syncicache()
456 msr = MFMSR(); in pmap_syncicache()
[all …]
H A Dfpu.c82 const register_t msr = mfmsr(); in fpu_state_load() local
83 mtmsr((msr & ~PSL_EE) | PSL_FP); in fpu_state_load()
89 mtmsr(msr); in fpu_state_load()
107 const register_t msr = mfmsr(); in fpu_state_save() local
108 mtmsr((msr & ~PSL_EE) | PSL_FP); in fpu_state_save()
114 mtmsr(msr); in fpu_state_save()
153 const register_t msr = mfmsr(); in fpu_get_fault_code() local
154 mtmsr((msr & ~PSL_EE) | PSL_FP); in fpu_get_fault_code()
172 mtmsr(msr); in fpu_get_fault_code()
H A Dkgdb_machdep.c86 u_int msr; in kgdb_acc()
95 __asm volatile ("mfmsr %0" : "=r"(msr)); in kgdb_acc()
96 if ((msr & PSL_DR) == 0) { in kgdb_acc()
127 if (BAT_VALID_P(batu,msr) && in kgdb_acc()
133 if (BAT_VALID_P(batu,msr) && in kgdb_acc()
139 if (BAT_VALID_P(batu,msr) && in kgdb_acc()
145 if (BAT_VALID_P(batu,msr) && in kgdb_acc()
264 gdb_regs[KGDB_PPC_MSR_REG] = regs->msr; in kgdb_getregs()
281 regs->msr = gdb_regs[KGDB_PPC_MSR_REG]; in kgdb_setregs()
85 u_int msr; kgdb_acc() local
/netbsd-src/sys/arch/rs6000/rs6000/
H A Dmachdep.c164 register_t savemsr, msr, savesr15; in setled()
167 msr = savemsr & ~PSL_DR; in setled()
168 __asm volatile ("mtmsr %0" : : "r"(msr)); in setled()
172 __asm volatile ("mtmsr %0" : : "r"(msr|PSL_DR)); in setled()
210 register_t savemsr, msr; in initppc() local
321 msr = savemsr & ~PSL_DR; in initppc()
322 __asm volatile ("mtmsr %0" : : "r"(msr)); in initppc()
324 __asm volatile ("mtmsr %0" : : "r"(msr|PSL_DR)); in initppc()
426 int msr; in cpu_startup() local
430 : "=r"(msr) : "K"(PSL_EE)); in cpu_startup()
[all …]
/netbsd-src/sys/arch/x86/acpi/
H A Dacpi_cpu_md.c151 uint64_t msr; in acpicpu_md_flags() local
248 if (rdmsr_safe(MSR_CMPHALT, &msr) != EFAULT) in acpicpu_md_flags()
270 if (rdmsr_safe(MSR_CMPHALT, &msr) != EFAULT) in acpicpu_md_flags()
493 struct acpicpu_pstate *ps, msr; in acpicpu_md_pstate_init() local
496 (void)memset(&msr, 0, sizeof(struct acpicpu_pstate)); in acpicpu_md_pstate_init()
523 msr.ps_control_addr = MSR_PERF_CTL; in acpicpu_md_pstate_init()
524 msr.ps_control_mask = __BITS(0, 15); in acpicpu_md_pstate_init()
526 msr.ps_status_addr = MSR_PERF_STATUS; in acpicpu_md_pstate_init()
527 msr.ps_status_mask = __BITS(0, 15); in acpicpu_md_pstate_init()
533 msr.ps_flags |= ACPICPU_FLAG_P_FIDVID; in acpicpu_md_pstate_init()
[all …]
/netbsd-src/sys/arch/arm/xscale/
H A Dpxa2x0_apm_asm.S170 msr cpsr, r1 /* Enter FIQ mode. */
175 msr cpsr, r1 /* Enter IRQ mode. */
180 msr cpsr, r1 /* Enter ABT mode. */
185 msr cpsr, r1 /* Enter UND mode. */
190 msr cpsr, r1 /* Enter SYS mode. */
194 msr cpsr, r1 /* Return to SVC mode. */
215 msr cpsr_c, r2 /* disable IRQ/FIQ */
222 msr cpsr_c, r2 /* enable IRQ/FIQ */
328 msr spsr, r0
333 msr cpsr, r1
[all …]
/netbsd-src/sys/arch/x86/include/
H A Dcpu_msr.h47 uint64_t msr = 0; in x86_msr_xcall() local
53 msr = rdmsr(msrdat->msr_type); in x86_msr_xcall()
55 msr &= ~msrdat->msr_mask; in x86_msr_xcall()
59 msr |= msrdat->msr_value; in x86_msr_xcall()
60 wrmsr(msrdat->msr_type, msr); in x86_msr_xcall()
/netbsd-src/sys/arch/evbppc/pmppc/dev/
H A Dif_cs_mainbus.c88 u_int32_t msr, nmsr;
90 __asm volatile("mfmsr %0" : "=r"(msr));
91 nmsr = (msr | PSL_FP) & ~(PSL_FE0 | PSL_FE1);
103 __asm volatile("mtmsr %0" :: "r"(msr));
116 u_int32_t msr, nmsr; in out64() local
121 __asm volatile("mfmsr %0" : "=r"(msr)); in out64()
122 nmsr = (msr | PSL_FP) & ~(PSL_FE0 | PSL_FE1); in out64()
134 __asm volatile("mtmsr %0" :: "r"(msr)); in out64()
194 u_int32_t msr, nmsr; in cs_io_write_multi_2() local
200 __asm volatile("mfmsr %0" : "=r"(msr)); in cs_io_write_multi_2()
[all …]
/netbsd-src/sys/arch/i386/i386/
H A Dlongrun.c70 uint64_t msr; member
95 uint64_t msr; in tmx86_init_longrun() local
98 if (rdmsr_safe(MSR_TMx86_LONGRUN, &msr) == EFAULT) in tmx86_init_longrun()
138 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN); in tmx86_get_longrun_mode()
186 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN); in tmx86_set_longrun_mode()
191 wrmsr(MSR_TMx86_LONGRUN, msrinfo.msr); in tmx86_set_longrun_mode()
194 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN_FLAGS); in tmx86_set_longrun_mode()
196 wrmsr(MSR_TMx86_LONGRUN_FLAGS, msrinfo.msr); in tmx86_set_longrun_mode()
/netbsd-src/sys/arch/arm/arm32/
H A Dspl.S66 msr cpsr_c, r2
70 msr cpsr_c, r4 /* Restore interrupts */
86 msr cpsr_c, r2
91 msr cpsr_all, r4
109 msr cpsr_c, r2
114 msr cpsr_c, r4
/netbsd-src/sys/arch/powerpc/include/oea/
H A Dspr.h322 register_t msr; in scom_read() local
325 msr = mfmsr(); in scom_read()
326 mtmsr(msr & ~PSL_EE); in scom_read()
333 mtmsr(msr); in scom_read()
342 register_t msr; in scom_write() local
344 msr = mfmsr(); in scom_write()
345 mtmsr(msr & ~PSL_EE); in scom_write()
353 mtmsr(msr); in scom_write()

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