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Searched refs:mm_boot_level_offset (Results 1 – 4 of 4) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
H A Damdgpu_vegam_smumgr.c339 uint32_t mm_boot_level_offset, mm_boot_level_value; in vegam_update_uvd_smc_table() local
347 mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + offsetof(SMU75_Discrete_DpmTable, in vegam_update_uvd_smc_table()
349 mm_boot_level_offset /= 4; in vegam_update_uvd_smc_table()
350 mm_boot_level_offset *= 4; in vegam_update_uvd_smc_table()
352 CGS_IND_REG__SMC, mm_boot_level_offset); in vegam_update_uvd_smc_table()
356 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value); in vegam_update_uvd_smc_table()
371 uint32_t mm_boot_level_offset, mm_boot_level_value; in vegam_update_vce_smc_table() local
382 mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + in vegam_update_vce_smc_table()
384 mm_boot_level_offset /= 4; in vegam_update_vce_smc_table()
385 mm_boot_level_offset *= 4; in vegam_update_vce_smc_table()
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H A Damdgpu_fiji_smumgr.c2373 uint32_t mm_boot_level_offset, mm_boot_level_value; in fiji_update_uvd_smc_table() local
2381 mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + offsetof(SMU73_Discrete_DpmTable, in fiji_update_uvd_smc_table()
2383 mm_boot_level_offset /= 4; in fiji_update_uvd_smc_table()
2384 mm_boot_level_offset *= 4; in fiji_update_uvd_smc_table()
2386 CGS_IND_REG__SMC, mm_boot_level_offset); in fiji_update_uvd_smc_table()
2390 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value); in fiji_update_uvd_smc_table()
2405 uint32_t mm_boot_level_offset, mm_boot_level_value; in fiji_update_vce_smc_table() local
2416 mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + in fiji_update_vce_smc_table()
2418 mm_boot_level_offset /= 4; in fiji_update_vce_smc_table()
2419 mm_boot_level_offset *= 4; in fiji_update_vce_smc_table()
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H A Damdgpu_polaris10_smumgr.c2185 uint32_t mm_boot_level_offset, mm_boot_level_value; in polaris10_update_uvd_smc_table() local
2193 mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + offsetof(SMU74_Discrete_DpmTable, in polaris10_update_uvd_smc_table()
2195 mm_boot_level_offset /= 4; in polaris10_update_uvd_smc_table()
2196 mm_boot_level_offset *= 4; in polaris10_update_uvd_smc_table()
2198 CGS_IND_REG__SMC, mm_boot_level_offset); in polaris10_update_uvd_smc_table()
2202 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value); in polaris10_update_uvd_smc_table()
2217 uint32_t mm_boot_level_offset, mm_boot_level_value; in polaris10_update_vce_smc_table() local
2228 mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + in polaris10_update_vce_smc_table()
2230 mm_boot_level_offset /= 4; in polaris10_update_vce_smc_table()
2231 mm_boot_level_offset *= 4; in polaris10_update_vce_smc_table()
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H A Damdgpu_tonga_smumgr.c2684 uint32_t mm_boot_level_offset, mm_boot_level_value; in tonga_update_uvd_smc_table() local
2692 mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + in tonga_update_uvd_smc_table()
2694 mm_boot_level_offset /= 4; in tonga_update_uvd_smc_table()
2695 mm_boot_level_offset *= 4; in tonga_update_uvd_smc_table()
2697 CGS_IND_REG__SMC, mm_boot_level_offset); in tonga_update_uvd_smc_table()
2702 mm_boot_level_offset, mm_boot_level_value); in tonga_update_uvd_smc_table()
2718 uint32_t mm_boot_level_offset, mm_boot_level_value; in tonga_update_vce_smc_table() local
2726 mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + in tonga_update_vce_smc_table()
2728 mm_boot_level_offset /= 4; in tonga_update_vce_smc_table()
2729 mm_boot_level_offset *= 4; in tonga_update_vce_smc_table()
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