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Searched refs:mmUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH_BASE_IDX (Results 1 – 2 of 2) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_5_offset.h890 #define mmUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH_BASE_IDX macro
H A Dvcn_2_0_0_offset.h845 #define mmUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH_BASE_IDX macro