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Searched refs:mmSPI_GDBG_WAVE_CNTL3_BASE_IDX (Results 1 – 2 of 2) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2721 #define mmSPI_GDBG_WAVE_CNTL3_BASE_IDX … macro
H A Dgc_9_2_1_offset.h2907 #define mmSPI_GDBG_WAVE_CNTL3_BASE_IDX … macro