Home
last modified time | relevance | path

Searched refs:mmSDMA0_RLC1_RB_AQL_CNTL_BASE_IDX (Results 1 – 5 of 5) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_1_offset.h437 #define mmSDMA0_RLC1_RB_AQL_CNTL_BASE_IDX … macro
H A Dsdma0_4_0_offset.h525 #define mmSDMA0_RLC1_RB_AQL_CNTL_BASE_IDX 0 macro
H A Dsdma0_4_2_offset.h521 #define mmSDMA0_RLC1_RB_AQL_CNTL_BASE_IDX … macro
H A Dsdma0_4_2_2_offset.h525 #define mmSDMA0_RLC1_RB_AQL_CNTL_BASE_IDX … macro
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_offset.h512 #define mmSDMA0_RLC1_RB_AQL_CNTL_BASE_IDX … macro