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Searched refs:mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX (Results 1 – 5 of 5) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_1_offset.h265 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX … macro
H A Dsdma0_4_0_offset.h269 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 macro
H A Dsdma0_4_2_offset.h265 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX … macro
H A Dsdma0_4_2_2_offset.h269 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX … macro
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_offset.h259 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX … macro