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Searched refs:mmSCRATCH_REG1_BASE_IDX (Results 1 – 6 of 6) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Dsoc15_common.h82 uint32_t r1 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1; \
104 uint32_t r2 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG2; \
105 uint32_t r3 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3; \
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_1_offset.h216 #define mmSCRATCH_REG1_BASE_IDX … macro
H A Dgc_9_0_offset.h4641 #define mmSCRATCH_REG1_BASE_IDX … macro
H A Dgc_9_1_offset.h4871 #define mmSCRATCH_REG1_BASE_IDX … macro
H A Dgc_9_2_1_offset.h4827 #define mmSCRATCH_REG1_BASE_IDX … macro
H A Dgc_10_1_0_offset.h7107 #define mmSCRATCH_REG1_BASE_IDX … macro