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Searched refs:mmSCL5_SCL_COEF_RAM_TAP_DATA (Results 1 – 6 of 6) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h4264 #define mmSCL5_SCL_COEF_RAM_TAP_DATA 0x4A41 macro
H A Ddce_8_0_d.h4833 #define mmSCL5_SCL_COEF_RAM_TAP_DATA 0x4a41 macro
H A Ddce_11_0_d.h5607 #define mmSCL5_SCL_COEF_RAM_TAP_DATA 0x4541 macro
H A Ddce_10_0_d.h5549 #define mmSCL5_SCL_COEF_RAM_TAP_DATA 0x4541 macro
H A Ddce_11_2_d.h6934 #define mmSCL5_SCL_COEF_RAM_TAP_DATA 0x4541 macro
H A Ddce_12_0_offset.h7868 #define mmSCL5_SCL_COEF_RAM_TAP_DATA … macro