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Searched refs:mmMPCC3_MPCC_SM_CONTROL_BASE_IDX (Results 1 – 3 of 3) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_1_0_offset.h5711 #define mmMPCC3_MPCC_SM_CONTROL_BASE_IDX … macro
H A Ddcn_1_0_offset.h5468 #define mmMPCC3_MPCC_SM_CONTROL_BASE_IDX … macro
H A Ddcn_2_0_0_offset.h6649 #define mmMPCC3_MPCC_SM_CONTROL_BASE_IDX … macro