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Searched refs:mmMP1_SMN_IH_SW_INT_BASE_IDX (Results 1 – 4 of 4) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/mp/
H A Dmp_10_0_offset.h331 #define mmMP1_SMN_IH_SW_INT_BASE_IDX … macro
H A Dmp_12_0_0_offset.h331 #define mmMP1_SMN_IH_SW_INT_BASE_IDX … macro
H A Dmp_11_0_offset.h335 #define mmMP1_SMN_IH_SW_INT_BASE_IDX … macro
H A Dmp_9_0_offset.h345 #define mmMP1_SMN_IH_SW_INT_BASE_IDX 0 macro