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Searched refs:mmDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX (Results 1 – 4 of 4) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_1_0_offset.h10876 #define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX … macro
H A Ddcn_1_0_offset.h9312 #define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX … macro
H A Ddcn_2_0_0_offset.h11963 #define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX … macro
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
H A Ddce_12_0_offset.h11081 #define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX … macro