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Searched refs:mmDC_GPIO_SYNCA_EN (Results 1 – 11 of 11) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
H A Damdgpu_fiji_baco.c54 { CMD_WRITE, mmDC_GPIO_SYNCA_EN, 0, 0, 0, 0x0 },
H A Damdgpu_ci_baco.c56 { CMD_WRITE, mmDC_GPIO_SYNCA_EN, 0, 0, 0, 0x0 },
H A Damdgpu_polaris_baco.c53 { CMD_WRITE, mmDC_GPIO_SYNCA_EN, 0, 0, 0, 0x0 },
H A Damdgpu_tonga_baco.c54 { CMD_WRITE, mmDC_GPIO_SYNCA_EN, 0, 0, 0, 0x0 },
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h1276 #define mmDC_GPIO_SYNCA_EN 0x1966 macro
H A Ddce_8_0_d.h1367 #define mmDC_GPIO_SYNCA_EN 0x1966 macro
H A Ddce_11_0_d.h1488 #define mmDC_GPIO_SYNCA_EN 0x4886 macro
H A Ddce_10_0_d.h1658 #define mmDC_GPIO_SYNCA_EN 0x4886 macro
H A Ddce_11_2_d.h1587 #define mmDC_GPIO_SYNCA_EN 0x4886 macro
H A Ddce_12_0_offset.h2030 #define mmDC_GPIO_SYNCA_EN macro
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_offset.h10557 #define mmDC_GPIO_SYNCA_EN macro