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Searched refs:mmCP_RB1_BASE (Results 1 – 11 of 11) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_d.h502 #define mmCP_RB1_BASE 0x3060 macro
H A Dgfx_7_0_d.h200 #define mmCP_RB1_BASE 0x3060 macro
H A Dgfx_7_2_d.h200 #define mmCP_RB1_BASE 0x3060 macro
H A Dgfx_8_0_d.h224 #define mmCP_RB1_BASE 0x3060 macro
H A Dgfx_8_1_d.h225 #define mmCP_RB1_BASE 0x3060 macro
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_gfx_v6_0.c2220 WREG32(mmCP_RB1_BASE, ring->gpu_addr >> 8); in gfx_v6_0_cp_compute_resume()
H A Damdgpu_gfx_v10_0.c2854 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr); in gfx_v10_0_cp_gfx_resume()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2445 #define mmCP_RB1_BASE … macro
H A Dgc_9_1_offset.h2722 #define mmCP_RB1_BASE … macro
H A Dgc_9_2_1_offset.h2660 #define mmCP_RB1_BASE … macro
H A Dgc_10_1_0_offset.h4788 #define mmCP_RB1_BASE … macro