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Searched refs:mmCP_INT_CNTL_RING1 (Results 1 – 11 of 11) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_gfx_v6_0.c3269 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1); in gfx_v6_0_set_compute_eop_interrupt_state()
3271 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl); in gfx_v6_0_set_compute_eop_interrupt_state()
3282 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1); in gfx_v6_0_set_compute_eop_interrupt_state()
3284 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl); in gfx_v6_0_set_compute_eop_interrupt_state()
H A Damdgpu_gfx_v10_0.c4823 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1); in gfx_v10_0_set_gfx_eop_interrupt_state()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_d.h441 #define mmCP_INT_CNTL_RING1 0x306B macro
H A Dgfx_7_0_d.h225 #define mmCP_INT_CNTL_RING1 0x306b macro
H A Dgfx_7_2_d.h225 #define mmCP_INT_CNTL_RING1 0x306b macro
H A Dgfx_8_0_d.h249 #define mmCP_INT_CNTL_RING1 0x306b macro
H A Dgfx_8_1_d.h250 #define mmCP_INT_CNTL_RING1 0x306b macro
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2467 #define mmCP_INT_CNTL_RING1 … macro
H A Dgc_9_1_offset.h2744 #define mmCP_INT_CNTL_RING1 … macro
H A Dgc_9_2_1_offset.h2682 #define mmCP_INT_CNTL_RING1 … macro
H A Dgc_10_1_0_offset.h4808 #define mmCP_INT_CNTL_RING1 … macro