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Searched refs:mmCM3_CM_MEM_PWR_STATUS (Results 1 – 3 of 3) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_1_0_offset.h5432 #define mmCM3_CM_MEM_PWR_STATUS … macro
H A Ddcn_1_0_offset.h5332 #define mmCM3_CM_MEM_PWR_STATUS … macro
H A Ddcn_2_0_0_offset.h6370 #define mmCM3_CM_MEM_PWR_STATUS … macro