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Searched refs:mmCM0_CM_MEM_PWR_STATUS2_BASE_IDX (Results 1 – 2 of 2) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_1_0_offset.h3829 #define mmCM0_CM_MEM_PWR_STATUS2_BASE_IDX … macro
H A Ddcn_2_0_0_offset.h4767 #define mmCM0_CM_MEM_PWR_STATUS2_BASE_IDX … macro