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Searched refs:mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_G (Results 1 – 2 of 2) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_1_0_offset.h3608 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_G … macro
H A Ddcn_2_0_0_offset.h4546 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_G … macro