Searched refs:mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW0 (Results 1 – 2 of 2) sorted by relevance
146 mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW0)); in xgpu_nv_mailbox_trans_msg()149 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW0), in xgpu_nv_mailbox_trans_msg()
590 #define mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW0 … macro