Searched refs:mips_cpu_arch (Results 1 – 5 of 5) sorted by relevance
110 if (mips_options.mips_cpu_arch < CPU_ARCH_MIPS2) in mips_netbsd_elf32_probe()114 if (mips_options.mips_cpu_arch < CPU_ARCH_MIPS3) in mips_netbsd_elf32_probe()118 if (mips_options.mips_cpu_arch < CPU_ARCH_MIPS4) in mips_netbsd_elf32_probe()122 if (mips_options.mips_cpu_arch < CPU_ARCH_MIPS5) in mips_netbsd_elf32_probe()178 if (mips_options.mips_cpu_arch & CPU_ARCH_MIPS64R2) { in coredump_elf32_setup()180 } else if (mips_options.mips_cpu_arch & CPU_ARCH_MIPS64) { in coredump_elf32_setup()182 } else if (mips_options.mips_cpu_arch & CPU_ARCH_MIPS32R2) { in coredump_elf32_setup()184 } else if (mips_options.mips_cpu_arch & CPU_ARCH_MIPS32) { in coredump_elf32_setup()186 } else if (mips_options.mips_cpu_arch & CPU_ARCH_MIPS5) { in coredump_elf32_setup()188 } else if (mips_options.mips_cpu_arch & CPU_ARCH_MIPS4) { in coredump_elf32_setup()[all …]
1179 opts->mips_cpu_arch = ct->cpu_isa; in mips_vector_init()1202 opts->mips_cpu_arch = CPU_ARCH_MIPS32; in mips_vector_init()1205 opts->mips_cpu_arch = CPU_ARCH_MIPS64; in mips_vector_init()1217 switch (opts->mips_cpu_arch) { in mips_vector_init()1219 opts->mips_cpu_arch = CPU_ARCH_MIPS32R2; in mips_vector_init()1222 opts->mips_cpu_arch = CPU_ARCH_MIPS64R2; in mips_vector_init()1226 "unknown!\n", opts->mips_cpu_arch, in mips_vector_init()1266 if (opts->mips_cpu_arch < 1) in mips_vector_init()1339 switch (opts->mips_cpu_arch) { in mips_vector_init()1422 printf("cpu_arch 0x%x: not supported\n", opts->mips_cpu_arch); in mips_vector_init()[all …]
453 if (mips_options.mips_cpu_arch >= CPU_ARCH_MIPS3) { in db_cp0dump_cmd()470 if (mips_options.mips_cpu_arch >= CPU_ARCH_MIPS3) { in db_cp0dump_cmd()
1498 printf("MIPS32/64 params: cpu arch: %d\n", opts->mips_cpu_arch); in mips_config_cache_modern()
111 u_int mips_cpu_arch; member312 #define CPUISMIPS3 ((mips_options.mips_cpu_arch & \316 #define CPUISMIPS4 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS4) != 0)317 #define CPUISMIPS5 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS5) != 0)318 #define CPUISMIPS32 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS32) != 0)319 #define CPUISMIPS32R2 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS32R2) != 0)320 #define CPUISMIPS64 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS64) != 0)321 #define CPUISMIPS64R2 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS64R2) != 0)322 #define CPUISMIPSNN ((mips_options.mips_cpu_arch & \324 #define CPUISMIPSNNR2 ((mips_options.mips_cpu_arch & \[all …]