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Searched refs:meta_req_width (Results 1 – 6 of 6) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn20/
H A Damdgpu_display_rq_dlg_calc_20v2.c361 unsigned int meta_req_width; in get_meta_and_pte_attr() local
482 meta_req_width = 1 << log2_meta_req_width; in get_meta_and_pte_attr()
491 meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1) in get_meta_and_pte_attr()
492 + meta_req_width; in get_meta_and_pte_attr()
493 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width; in get_meta_and_pte_attr()
542 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width; in get_meta_and_pte_attr()
H A Damdgpu_display_rq_dlg_calc_20.c361 unsigned int meta_req_width; in get_meta_and_pte_attr() local
482 meta_req_width = 1 << log2_meta_req_width; in get_meta_and_pte_attr()
491 meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1) in get_meta_and_pte_attr()
492 + meta_req_width; in get_meta_and_pte_attr()
493 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width; in get_meta_and_pte_attr()
542 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width; in get_meta_and_pte_attr()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/
H A Damdgpu_dml1_display_rq_dlg_calc.c570 unsigned int meta_req_width; in get_surf_rq_param() local
713 meta_req_width = 1 << log2_meta_req_width; in get_surf_rq_param()
723 meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1) in get_surf_rq_param()
724 + meta_req_width; in get_surf_rq_param()
725 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width; in get_surf_rq_param()
769 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width; in get_surf_rq_param()
H A Ddisplay_mode_vba.h588 unsigned int meta_req_width[DC__NUM_DPP__MAX]; member
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn21/
H A Damdgpu_display_rq_dlg_calc_21.c351 unsigned int meta_req_width; in get_meta_and_pte_attr() local
476 meta_req_width = 1 << log2_meta_req_width; in get_meta_and_pte_attr()
485 meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1) in get_meta_and_pte_attr()
486 + meta_req_width; in get_meta_and_pte_attr()
487 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width; in get_meta_and_pte_attr()
539 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width; in get_meta_and_pte_attr()
H A Damdgpu_display_mode_vba_21.c442 unsigned int meta_req_width[],
1965 &locals->meta_req_width[k], in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2528 locals->meta_req_width, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
4556 &locals->meta_req_width[k], in dml21_ModeSupportAndSystemConfigurationFull()
5844 unsigned int meta_req_width[], in CalculateMetaAndPTETimes() argument
5919 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width[k]; in CalculateMetaAndPTETimes()