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Searched refs:memory_level (Results 1 – 4 of 4) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
H A Damdgpu_iceland_smumgr.c1235 SMU71_Discrete_MemoryLevel *memory_level in iceland_populate_single_memory_level() argument
1247 hwmgr->dyn_state.vddc_dependency_on_mclk, memory_clock, &memory_level->MinVddc); in iceland_populate_single_memory_level()
1253 memory_level->MinVddci = memory_level->MinVddc; in iceland_populate_single_memory_level()
1258 &memory_level->MinVddci); in iceland_populate_single_memory_level()
1263 memory_level->MinVddcPhases = 1; in iceland_populate_single_memory_level()
1267 memory_clock, &memory_level->MinVddcPhases); in iceland_populate_single_memory_level()
1270 memory_level->EnabledForThrottle = 1; in iceland_populate_single_memory_level()
1271 memory_level->EnabledForActivity = 0; in iceland_populate_single_memory_level()
1272 memory_level->UpHyst = data->current_profile_setting.mclk_up_hyst; in iceland_populate_single_memory_level()
1273 memory_level->DownHyst = data->current_profile_setting.mclk_down_hyst; in iceland_populate_single_memory_level()
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H A Damdgpu_ci_smumgr.c1180 SMU7_Discrete_MemoryLevel *memory_level in ci_populate_single_memory_level() argument
1192 hwmgr->dyn_state.vddc_dependency_on_mclk, memory_clock, &memory_level->MinVddc); in ci_populate_single_memory_level()
1201 &memory_level->MinVddci); in ci_populate_single_memory_level()
1210 &memory_level->MinMvdd); in ci_populate_single_memory_level()
1215 memory_level->MinVddcPhases = 1; in ci_populate_single_memory_level()
1219 memory_clock, &memory_level->MinVddcPhases); in ci_populate_single_memory_level()
1222 memory_level->EnabledForThrottle = 1; in ci_populate_single_memory_level()
1223 memory_level->EnabledForActivity = 1; in ci_populate_single_memory_level()
1224 memory_level->UpH = data->current_profile_setting.mclk_up_hyst; in ci_populate_single_memory_level()
1225 memory_level->DownH = data->current_profile_setting.mclk_down_hyst; in ci_populate_single_memory_level()
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H A Damdgpu_tonga_smumgr.c967 SMU72_Discrete_MemoryLevel *memory_level in tonga_populate_single_memory_level() argument
991 &memory_level->MinVoltage, &mvdd); in tonga_populate_single_memory_level()
1000 memory_level->MinMvdd = data->vbios_boot_state.mvdd_bootup_value; in tonga_populate_single_memory_level()
1002 memory_level->MinMvdd = mvdd; in tonga_populate_single_memory_level()
1004 memory_level->EnabledForThrottle = 1; in tonga_populate_single_memory_level()
1005 memory_level->EnabledForActivity = 0; in tonga_populate_single_memory_level()
1006 memory_level->UpHyst = data->current_profile_setting.mclk_up_hyst; in tonga_populate_single_memory_level()
1007 memory_level->DownHyst = data->current_profile_setting.mclk_down_hyst; in tonga_populate_single_memory_level()
1008 memory_level->VoltageDownHyst = 0; in tonga_populate_single_memory_level()
1011 memory_level->ActivityLevel = data->current_profile_setting.mclk_activity; in tonga_populate_single_memory_level()
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/netbsd-src/sys/external/bsd/drm2/dist/drm/radeon/
H A Dradeon_ci_dpm.c2883 SMU7_Discrete_MemoryLevel *memory_level) in ci_populate_single_memory_level() argument
2892 memory_clock, &memory_level->MinVddc); in ci_populate_single_memory_level()
2900 memory_clock, &memory_level->MinVddci); in ci_populate_single_memory_level()
2908 memory_clock, &memory_level->MinMvdd); in ci_populate_single_memory_level()
2913 memory_level->MinVddcPhases = 1; in ci_populate_single_memory_level()
2919 &memory_level->MinVddcPhases); in ci_populate_single_memory_level()
2921 memory_level->EnabledForThrottle = 1; in ci_populate_single_memory_level()
2922 memory_level->UpH = 0; in ci_populate_single_memory_level()
2923 memory_level->DownH = 100; in ci_populate_single_memory_level()
2924 memory_level->VoltageDownH = 0; in ci_populate_single_memory_level()
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